| /freebsd/sys/contrib/device-tree/Bindings/input/ |
| H A D | gpio-matrix-keypad.txt | 1 * GPIO driven matrix keypad device tree bindings
3 GPIO driven matrix keypad is used to interface a SoC with a matrix keypad.
4 The matrix keypad supports multiple row and column lines, a key can be
6 keypad can sense a key-press and key-release by means of GPIO lines and
7 report the event using GPIO interrupts to the cpu.
10 - compatible: Should be "gpio-matrix-keypad"
11 - row-gpios: List of gpios used as row lines. The gpio specifier
12 for this property depends on the gpio controller to
13 which these row lines are connected.
14 - col-gpios: List of gpios used as column lines. The gpio specifier
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-mmio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic MMIO GPIO
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
14 Some simple GPIO controllers may consist of a single data register or a pair
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
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| H A D | intel,ixp4xx-gpio.txt | 1 Intel IXP4xx XScale Networking Processors GPIO
3 This GPIO controller is found in the Intel IXP4xx processors.
4 It supports 16 GPIO lines.
6 The interrupt portions of the GPIO controller is hierarchical:
7 the synchronous edge detector is part of the GPIO block, but the
10 the first 12 GPIO lines to 12 system interrupts.
12 The remaining 4 GPIO lines can not be used for receiving
15 The interrupt parent of this GPIO controller must be the
20 - compatible : Should be
21 "intel,ixp4xx-gpio"
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| H A D | brcm,brcmstb-gpio.txt | 1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
14 the brcmstb GPIO controller registers
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
22 Specifies that the node is a GPIO controller.
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| H A D | nxp,pcf8575.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nxp,pcf8575.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCF857x-compatible I/O expanders
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
14 driven high by a pull-up current source or driven low to ground. This
25 - maxim,max7328
26 - maxim,max7329
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| H A D | gpio-pcf857x.txt | 1 * PCF857x-compatible I/O expanders
3 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
4 driven high by a pull-up current source or driven low to ground. This combines
14 - compatible: should be one of the following.
15 - "maxim,max7328": For the Maxim MAX7378
16 - "maxim,max7329": For the Maxim MAX7329
17 - "nxp,pca8574": For the NXP PCA8574
18 - "nxp,pca8575": For the NXP PCA8575
19 - "nxp,pca9670": For the NXP PCA9670
20 - "nxp,pca9671": For the NXP PCA9671
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| H A D | gpio_atmel.txt | 1 * Atmel GPIO controller (PIO)
4 - compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5.
5 - reg: Should contain GPIO controller registers location and length
6 - interrupts: Should be the port interrupt shared by all the pins.
7 - #gpio-cells: Should be two. The first cell is the pin number and
8 the second cell is used to specify optional parameters to declare if the GPIO
9 is active high or low. See gpio.txt.
10 - gpio-controller: Marks the device node as a GPIO controller.
11 - interrupt-controller: Marks the device node as an interrupt controller.
12 - #interrupt-cells: Should be two. The first cell is the pin number and the
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| H A D | gpio.txt | 1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
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| H A D | brcm,brcmstb-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB "UPG GIO" GPIO controller
10 The controller's registers are organized as sets of eight 32-bit
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | msm8916-pins.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 blsp1_uart1_default: blsp1-uart1-default-state {
13 drive-strength = <16>;
14 bias-disable;
17 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
19 function = "gpio";
21 drive-strength = <2>;
22 bias-pull-down;
25 blsp1_uart2_default: blsp1-uart2-default-state {
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
14 dedicated GPIO lines.
17 - $ref: /schemas/spi/spi-controller.yaml#
21 const: spi-gpio
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| /freebsd/sys/dev/ath/ath_hal/ar5212/ |
| H A D | ar5212_gpio.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
32 #define AR_NUM_GPIO 6 /* 6 GPIO pins */
33 #define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */
36 * Configure GPIO Output lines
39 ar5212GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type) in ar5212GpioCfgOutput() argument
41 HALASSERT(gpio < AR_NUM_GPIO); in ar5212GpioCfgOutput()
48 OS_REG_READ(ah, AR_GPIOCR) | AR_GPIOCR_CR_A(gpio)); in ar5212GpioCfgOutput()
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| /freebsd/sys/dev/ath/ath_hal/ar5312/ |
| H A D | ar5312_gpio.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
31 #define AR_NUM_GPIO 6 /* 6 GPIO pins */
32 #define AR5312_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */
35 * Configure GPIO Output lines
38 ar5312GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type) in ar5312GpioCfgOutput() argument
40 uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh)); in ar5312GpioCfgOutput()
42 HALASSERT(gpio < AR_NUM_GPIO); in ar5312GpioCfgOutput()
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| H A D | ar5315_gpio.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
31 #define AR_NUM_GPIO 7 /* 6 GPIO pins */
32 #define AR5315_GPIOD_MASK 0x0000007F /* GPIO data reg r/w mask */
35 * Configure GPIO Output lines
38 ar5315GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type) in ar5315GpioCfgOutput() argument
40 uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh)); in ar5315GpioCfgOutput()
42 HALASSERT(gpio < AR_NUM_GPIO); in ar5315GpioCfgOutput()
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| /freebsd/sys/contrib/device-tree/Bindings/auxdisplay/ |
| H A D | hit,hd44780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
14 LCDs that can display one or more lines of text. It exposes an M6800 bus
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
16 GPIO expander it is possible to use the driver with one of the popular I2C
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
27 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
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| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | nxp,sc16is7xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP SC16IS7xx Advanced Universal Asynchronous Receiver-Transmitter (UART)
10 - Hugo Villeneuve <hvilleneuve@dimonoff.com>
15 - nxp,sc16is740
16 - nxp,sc16is741
17 - nxp,sc16is750
18 - nxp,sc16is752
19 - nxp,sc16is760
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| /freebsd/sys/contrib/device-tree/src/arm64/bitmain/ |
| H A D | bm1880-sophon-edge.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
12 * GPIO name legend: proper name = the GPIO line is used as GPIO
15 * "[PER]" = pin is muxed for [peripheral] (not GPIO)
19 * Line names are taken from the schematic "sophon-edge-schematics"
22 * For the lines routed to the external connectors the
23 * lines are named after the 96Boards CE Specification 1.0,
29 * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
30 * are the only ones actually used for GPIO.
34 compatible = "bitmain,sophon-edge", "bitmain,bm1880";
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| /freebsd/sys/dev/ath/ath_hal/ar5416/ |
| H A D | ar5416_gpio.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
32 * Configure GPIO Output Mux control
35 cfgOutputMux(struct ath_hal *ah, uint32_t gpio, uint32_t type) in cfgOutputMux() argument
40 HALDEBUG(ah, HAL_DEBUG_GPIO, "%s: gpio=%d, type=%d\n", in cfgOutputMux()
41 __func__, gpio, type); in cfgOutputMux()
43 /* each MUX controls 6 GPIO pins */ in cfgOutputMux()
44 if (gpio > 11) in cfgOutputMux()
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| /freebsd/sys/contrib/device-tree/Bindings/timestamp/ |
| H A D | nvidia,tegra194-hte.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dipen Patel <dipenp@nvidia.com>
14 known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip
15 IRQ lines for the state change respectively, upon detection it will record
18 to enable or disable for the hardware timestamping. The GTE GPIO monitors
19 GPIO lines from the AON (always on) GPIO controller.
24 - nvidia,tegra194-gte-aon
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| /freebsd/sys/contrib/device-tree/src/arm64/actions/ |
| H A D | s900-bubblegum-96.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "ucrobotics,bubblegum-96", "actions,s900";
12 model = "Bubblegum-96";
22 stdout-path = "serial5:115200n8";
31 vcc_3v1: vcc-3v1 {
32 compatible = "regulator-fixed";
33 regulator-name = "fixed-3.1V";
34 regulator-min-microvolt = <3100000>;
35 regulator-max-microvolt = <3100000>;
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | cec-gpio.txt | 1 * HDMI CEC GPIO driver
3 The HDMI CEC GPIO module supports CEC implementations where the CEC line
4 is hooked up to a pull-up GPIO line and - optionally - the HPD line is
5 hooked up to another GPIO line.
8 5V lines it is 5.3V. So you may need some sort of level conversion circuitry
9 when connecting them to a GPIO line.
12 - compatible: value must be "cec-gpio".
13 - cec-gpios: gpio that the CEC line is connected to. The line should be
19 - hdmi-phandle - phandle to the HDMI controller, see also cec.txt.
24 - hpd-gpios: gpio that the HPD line is connected to.
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| /freebsd/sys/contrib/device-tree/Bindings/connector/ |
| H A D | usb-connector.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ro
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| /freebsd/sys/contrib/device-tree/src/arm64/hisilicon/ |
| H A D | hi3670-hikey970.dts | 1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
14 #include "hikey970-pinctrl.dtsi"
15 #include "hikey970-pmic.dtsi"
19 compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
34 stdout-path = "serial6:115200n8";
43 wlan_en: wlan-en-1-8v {
44 compatible = "regulator-fixed";
45 regulator-name = "wlan-en-regulator";
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_gpio.c | 33 * Configure GPIO Output Mux control
38 u_int32_t gpio, in ar9340_soc_gpio_cfg_output_mux() argument
59 * To use GPIO pins 0 and 1 for controling antennas, JTAG needs to disabled. in ar9340_soc_gpio_cfg_output_mux()
61 if (gpio <= MAX_JTAG_GPIO_PIN) { in ar9340_soc_gpio_cfg_output_mux()
67 out_func = gpio / 4; in ar9340_soc_gpio_cfg_output_mux()
68 shift = (gpio % 4); in ar9340_soc_gpio_cfg_output_mux()
75 flags &= ~(1 << gpio); in ar9340_soc_gpio_cfg_output_mux()
82 ar9300_gpio_cfg_output_mux(struct ath_hal *ah, u_int32_t gpio, u_int32_t type) in ar9300_gpio_cfg_output_mux() argument
87 /* each MUX controls 6 GPIO pins */ in ar9300_gpio_cfg_output_mux()
88 if (gpio > 11) { in ar9300_gpio_cfg_output_mux()
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | ste-href-tvk1281618-r2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/input/input.h>
11 compatible = "gpio-key
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