| /linux/arch/x86/kernel/apic/ |
| H A D | init.c | 17 DEFINE_APIC_CALL(eoi);
45 apply_override(eoi); in restore_override_callbacks()
66 update_call(eoi); in update_static_calls()
86 apic->native_eoi = apic->eoi; in apic_setup_apic_calls()
101 /* Copy the original eoi() callback as KVM/HyperV might overwrite it */ in apic_install_driver()
103 apic->native_eoi = apic->eoi; in apic_install_driver()
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| H A D | x2apic_savic.c | 311 if (WARN_ONCE(vec == -1, "EOI write while no active interrupt in APIC_ISR")) in savic_eoi()
318 * Propagate the EOI write to the hypervisor for level-triggered in savic_eoi()
421 .eoi = savic_eoi,
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| /linux/arch/powerpc/sysdev/xics/ |
| H A D | icp-opal.c | 33 * We take the ipi irq but and never return so we need to EOI the IPI, in icp_opal_flush_ipi()
82 /* We might learn about it later, so EOI it */ in icp_opal_get_irq()
115 * EOI tells us whether there are more interrupts to fetch. in icp_opal_eoi()
169 /* EOI the interrupt */ in icp_opal_flush_interrupt()
177 .eoi = icp_opal_eoi,
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| H A D | icp-hv.c | 53 pr_err("%s: bad return code eoi xirr=0x%x returned %ld\n", in icp_hv_set_xirr()
94 * need to EOI the IPI, but want to leave our priority 0 in icp_hv_flush_ipi()
122 /* We might learn about it later, so EOI it */ in icp_hv_get_irq()
155 .eoi = icp_hv_eoi,
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| /linux/drivers/xen/xen-pciback/ |
| H A D | pciback_ops.c | 295 bool eoi = true; in xen_pcibk_test_and_schedule_op() local
301 eoi = false; in xen_pcibk_test_and_schedule_op()
308 eoi = false; in xen_pcibk_test_and_schedule_op()
311 /* EOI if there was nothing to do. */ in xen_pcibk_test_and_schedule_op()
312 if (eoi) in xen_pcibk_test_and_schedule_op()
412 bool eoi; in xen_pcibk_handle_event() local
418 eoi = test_and_set_bit(_EOI_pending, &pdev->flags); in xen_pcibk_handle_event()
419 WARN(eoi, "IRQ while EOI pending\n"); in xen_pcibk_handle_event()
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| /linux/arch/x86/kvm/ |
| H A D | ioapic.c | 185 * If no longer has pending EOI in LAPICs, update in ioapic_lazy_update_eoi()
186 * EOI for this vector. in ioapic_lazy_update_eoi()
211 * AMD SVM AVIC accelerate EOI write iff the interrupt is edge in ioapic_set_irq()
213 * to receive the EOI. In this case, we do a lazy update of the in ioapic_set_irq()
214 * pending EOI when trying to set IOAPIC irq. in ioapic_set_irq()
223 * us if the interrupt is waiting for an EOI. in ioapic_set_irq()
226 * if it has been already ack-ed via EOI because coalesced RTC in ioapic_set_irq()
228 * EOI manually for the RTC interrupt. in ioapic_set_irq()
274 /* Make sure we see any missing RTC EOI */ in kvm_ioapic_scan_entry()
383 * explicit EOI on IOAPICs that don't have the EOI register. in ioapic_write_indirect()
[all …]
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| /linux/drivers/irqchip/ |
| H A D | irq-i8259.c | 131 * first, _then_ send the EOI, and the order of EOI
164 outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ in mask_and_ack_8259A()
165 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ in mask_and_ack_8259A()
169 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ in mask_and_ack_8259A()
245 if (auto_eoi) /* master does Auto EOI */ in init_8259A()
247 else /* master expects normal EOI */ in init_8259A()
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| H A D | irq-clps711x.c | 40 phys_addr_t eoi; member
95 writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hwirq].eoi); in clps711x_intc_eoi()
139 } else if (clps711x_irqs[hw].eoi) { in clps711x_intc_irq_map()
144 if (clps711x_irqs[hw].eoi) in clps711x_intc_irq_map()
145 writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hw].eoi); in clps711x_intc_irq_map()
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-devices-xenbus | 19 Summed up time in jiffies the EOI of an interrupt for a Xen
30 trigger delayed EOI processing.
37 before delayed EOI processing is triggered for a Xen pv
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| /linux/drivers/xen/events/ |
| H A D | events_base.c | 113 unsigned short eoi_cpu; /* EOI must happen on this cpu-1 */
115 u64 eoi_time; /* Time in jiffies when to EOI. */
557 struct lateeoi_work *eoi = &per_cpu(lateeoi, info->eoi_cpu); in lateeoi_list_del() local
560 spin_lock_irqsave(&eoi->eoi_list_lock, flags); in lateeoi_list_del()
562 spin_unlock_irqrestore(&eoi->eoi_list_lock, flags); in lateeoi_list_del()
567 struct lateeoi_work *eoi = &per_cpu(lateeoi, info->eoi_cpu); in lateeoi_list_add() local
578 spin_lock_irqsave(&eoi->eoi_list_lock, flags); in lateeoi_list_add()
580 elem = list_first_entry_or_null(&eoi->eoi_list, struct irq_info, in lateeoi_list_add()
583 list_add(&info->eoi_list, &eoi->eoi_list); in lateeoi_list_add()
585 &eoi->delayed, delay); in lateeoi_list_add()
[all …]
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| /linux/Documentation/virt/kvm/x86/ |
| H A D | msr.rst | 318 injection. Value of 1 means that guest can skip writing EOI to the apic
320 EOI by clearing the bit in guest memory - this location will
322 Value of 0 means that the EOI write is required.
325 the APIC EOI write anyway.
336 whether it can skip EOI apic write and between guest
337 clearing it to signal EOI to the hypervisor,
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| /linux/drivers/staging/gpib/uapi/ |
| H A D | gpib.h | 47 END = (1 << END_NUM), /* EOI or EOS encountered */
61 XEOS = 0x800, /* assert EOI when EOS char is sent */
83 BUS_EOI = 0x8000 /* EOI line status bit */
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| /linux/arch/powerpc/kvm/ |
| H A D | book3s_xive.c | 97 /* If the XIVE supports the new "store EOI facility, use it */ in xive_vm_source_eoi()
102 * For LSIs the HW EOI cycle is used rather than PQ bits, in xive_vm_source_eoi()
111 * Otherwise for EOI, we use the special MMIO that does in xive_vm_source_eoi()
113 * except for LSIs where we use the "EOI cycle" special in xive_vm_source_eoi()
166 * Snapshot the queue page. The test further down for EOI in xive_vm_scan_interrupts()
169 * to miss an EOI. in xive_vm_scan_interrupts()
183 * we EOI it now, thus re-enabling reception of a new in xive_vm_scan_interrupts()
255 * If this is an EOI that's it, no CPPR adjustment done here, in xive_vm_scan_interrupts()
441 /* If it's not an LSI, set PQ to 11 the EOI will force a resend */ in xive_vm_scan_for_rerouted_irqs()
445 /* EOI the source */ in xive_vm_scan_for_rerouted_irqs()
[all …]
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| H A D | book3s_hv_rm_xics.c | 685 * ICS EOI handling: For LSI, if P bit is still set, we need to in ics_rm_eoi()
744 * ICP State: EOI in xics_rm_h_eoi()
746 * Note: If EOI is incorrectly used by SW to lower the CPPR in xics_rm_h_eoi()
751 * The sending of an EOI to the ICS is handled after the in xics_rm_h_eoi()
759 /* IPIs have no EOI */ in xics_rm_h_eoi()
780 /* EOI it */ in icp_eoi()
880 /* EOI the interrupt */ in kvmppc_deliver_irq_passthru()
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| /linux/arch/powerpc/sysdev/xive/ |
| H A D | common.c | 351 * as a "replay" because EOI decided there was still something in xive_get_irq()
359 * entry (on HW interrupt) from a replay triggered by EOI, in xive_get_irq()
380 * After EOI'ing an interrupt, we need to re-check the queue
392 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio); in xive_do_queue_eoi()
398 * EOI an interrupt at the source. There are several methods
407 /* If the XIVE supports the new "store EOI facility, use it */ in xive_do_source_eoi()
414 * For LSIs, we use the "EOI cycle" special load rather than in xive_do_source_eoi()
437 /* irq_chip eoi callback, called with irq descriptor lock held */
447 * EOI the source if it hasn't been disabled and hasn't in xive_irq_eoi()
826 * 11, then perform an EOI. in xive_irq_retrigger()
[all …]
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | mstar,mst-intc.yaml | 42 mstar,intc-no-eoi:
44 Mark this controller has no End Of Interrupt(EOI) implementation.
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| /linux/arch/powerpc/include/asm/ |
| H A D | xive-regs.h | 14 * to a queue and is waiting for an EOI). Q indicates that the
20 * When doing an EOI, the Q bit will indicate if the interrupt
28 * Additionally, some ESB pages support doing an EOI via a
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| /linux/arch/x86/kernel/cpu/ |
| H A D | acrn.c | 48 * The hypervisor requires that the APIC EOI should be acked. in DEFINE_IDTENTRY_SYSVEC()
49 * If the APIC EOI is not acked, the APIC ISR bit for the in DEFINE_IDTENTRY_SYSVEC()
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| /linux/arch/mips/sibyte/sb1250/ |
| H A D | irq.c | 161 * Generate EOI. For Pass 1 parts, EOI is a nop. For in ack_sb1250_irq()
163 * this EOI shouldn't hurt. If they are in ack_sb1250_irq()
164 * level-sensitive, the EOI is required. in ack_sb1250_irq()
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| /linux/Documentation/core-api/ |
| H A D | genericirq.rst | 44 - Fast EOI type
235 Default Fast EOI IRQ flow handler
239 which only need an EOI at the end of the handler.
304 EOI Edge IRQ flow handler
359 - ``irq_eoi`` - Optional, required for EOI flow handlers
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| /linux/arch/m68k/atari/ |
| H A D | ataints.c | 275 st_mfp.vec_adr = 0x48; /* Software EOI-Mode */ in atari_init_IRQ()
277 st_mfp.vec_adr = 0x40; /* Automatic EOI-Mode */ in atari_init_IRQ()
286 tt_mfp.vec_adr = 0x58; /* Software EOI-Mode */ in atari_init_IRQ()
288 tt_mfp.vec_adr = 0x50; /* Automatic EOI-Mode */ in atari_init_IRQ()
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| /linux/arch/mips/sibyte/bcm1480/ |
| H A D | irq.c | 176 * Generate EOI. For Pass 1 parts, EOI is a nop. For in ack_bcm1480_irq()
178 * this EOI shouldn't hurt. If they are in ack_bcm1480_irq()
179 * level-sensitive, the EOI is required. in ack_bcm1480_irq()
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| /linux/arch/powerpc/sysdev/ |
| H A D | i8259.c | 85 outb(0x20, 0xA0); /* Non-specific EOI */ in i8259_mask_and_ack_irq()
86 outb(0x20, 0x20); /* Non-specific EOI to cascade */ in i8259_mask_and_ack_irq()
91 outb(0x20, 0x20); /* Non-specific EOI */ in i8259_mask_and_ack_irq()
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| /linux/arch/parisc/include/asm/ |
| H A D | superio.h | 34 #define OCW2_EOI 0x20 /* Non-specific EOI */
35 #define OCW2_SEOI 0x60 /* Specific EOI */
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| /linux/drivers/parisc/ |
| H A D | eisa.c | 211 /* mask irq and write eoi */ in eisa_irq()
215 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */ in eisa_irq()
216 eisa_out8(0x62, 0x20); /* 'Specific EOI' to master-IRQ2 */ in eisa_irq()
221 eisa_out8(0x60|irq, 0x20); /* 'Specific EOI' to master */ in eisa_irq()
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