xref: /linux/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml (revision 68993ced0f618e36cf33388f1e50223e5e6e78cc) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Eswin EIC7700 SOC Eth Controller
8
9maintainers:
10  - Shuang Liang <liangshuang@eswincomputing.com>
11  - Zhi Li <lizhi2@eswincomputing.com>
12  - Shangjuan Wei <weishangjuan@eswincomputing.com>
13
14description:
15  Platform glue layer implementation for STMMAC Ethernet driver.
16
17select:
18  properties:
19    compatible:
20      contains:
21        enum:
22          - eswin,eic7700-qos-eth
23  required:
24    - compatible
25
26allOf:
27  - $ref: snps,dwmac.yaml#
28
29properties:
30  compatible:
31    items:
32      - const: eswin,eic7700-qos-eth
33      - const: snps,dwmac-5.20
34
35  reg:
36    maxItems: 1
37
38  interrupts:
39    maxItems: 1
40
41  interrupt-names:
42    const: macirq
43
44  clocks:
45    items:
46      - description: AXI clock
47      - description: Configuration clock
48      - description: GMAC main clock
49      - description: Tx clock
50
51  clock-names:
52    items:
53      - const: axi
54      - const: cfg
55      - const: stmmaceth
56      - const: tx
57
58  resets:
59    maxItems: 1
60
61  reset-names:
62    items:
63      - const: stmmaceth
64
65  rx-internal-delay-ps:
66    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
67
68  tx-internal-delay-ps:
69    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
70
71  eswin,hsp-sp-csr:
72    description:
73      HSP CSR is to control and get status of different high-speed peripherals
74      (such as Ethernet, USB, SATA, etc.) via register, which can tune
75      board-level's parameters of PHY, etc.
76
77      Additional background information about the High-Speed Subsystem
78      and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
79      of the EIC7700X SoC Technical Reference Manual, Part 4
80      (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is
81      publicly available at
82      https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
83
84      This reference is provided for background information only.
85    $ref: /schemas/types.yaml#/definitions/phandle-array
86    items:
87      - items:
88          - description: Phandle to HSP(High-Speed Peripheral) device
89          - description: Offset of phy control register for internal
90                         or external clock selection
91          - description: Offset of AXI clock controller Low-Power request
92                         register
93          - description: Offset of register controlling TX/RX clock delay
94          - description: Optional offset of register controlling TXD delay
95          - description: Optional offset of register controlling RXD delay
96
97required:
98  - compatible
99  - reg
100  - clocks
101  - clock-names
102  - interrupts
103  - interrupt-names
104  - phy-mode
105  - resets
106  - reset-names
107  - rx-internal-delay-ps
108  - tx-internal-delay-ps
109  - eswin,hsp-sp-csr
110
111unevaluatedProperties: false
112
113examples:
114  - |
115    ethernet@50400000 {
116        compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
117        reg = <0x50400000 0x10000>;
118        clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
119                <&d0_clock 193>;
120        clock-names = "axi", "cfg", "stmmaceth", "tx";
121        interrupt-parent = <&plic>;
122        interrupts = <61>;
123        interrupt-names = "macirq";
124        phy-mode = "rgmii-id";
125        phy-handle = <&phy0>;
126        resets = <&reset 95>;
127        reset-names = "stmmaceth";
128        rx-internal-delay-ps = <200>;
129        tx-internal-delay-ps = <200>;
130        eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>;
131        snps,axi-config = <&stmmac_axi_setup>;
132        snps,aal;
133        snps,fixed-burst;
134        snps,tso;
135        stmmac_axi_setup: stmmac-axi-config {
136            snps,blen = <0 0 0 0 16 8 4>;
137            snps,rd_osr_lmt = <2>;
138            snps,wr_osr_lmt = <2>;
139        };
140    };
141