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/linux/drivers/dma/dw-edma/
H A Ddw-edma-v0-debugfs.c12 #include "dw-edma-v0-debugfs.h"
13 #include "dw-edma-v0-regs.h"
14 #include "dw-edma-core.h"
16 #define REGS_ADDR(dw, name) \ argument
18 struct dw_edma_v0_regs __iomem *__regs = (dw)->chip->reg_base; \
23 #define REGS_CH_ADDR(dw, name, _dir, _ch) \ argument
27 if ((dw)->chip->mf == EDMA_MF_EDMA_LEGACY) \
28 __ch_regs = REGS_ADDR(dw, type.legacy.ch); \
30 __ch_regs = REGS_ADDR(dw, type.unroll.ch[_ch].rd); \
32 __ch_regs = REGS_ADDR(dw, type.unroll.ch[_ch].wr); \
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H A Ddw-edma-v0-core.c13 #include "dw-edma-core.h"
14 #include "dw-edma-v0-core.h"
15 #include "dw-edma-v0-regs.h"
16 #include "dw-edma-v0-debugfs.h"
28 static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) in __dw_regs() argument
30 return dw->chip->reg_base; in __dw_regs()
33 #define SET_32(dw, name, value) \ argument
34 writel(value, &(__dw_regs(dw)->name))
36 #define GET_32(dw, name) \ argument
37 readl(&(__dw_regs(dw)->name))
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H A Ddw-hdma-v0-debugfs.c12 #include "dw-hdma-v0-debugfs.h"
13 #include "dw-hdma-v0-regs.h"
14 #include "dw-edma-core.h"
16 #define REGS_ADDR(dw, name) \ argument
18 struct dw_hdma_v0_regs __iomem *__regs = (dw)->chip->reg_base; \
23 #define REGS_CH_ADDR(dw, name, _dir, _ch) \ argument
28 __ch_regs = REGS_ADDR(dw, ch[_ch].rd); \
30 __ch_regs = REGS_ADDR(dw, ch[_ch].wr); \
35 #define CTX_REGISTER(dw, name, dir, ch) \ argument
36 {#name, REGS_CH_ADDR(dw, name, dir, ch)}
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H A Ddw-hdma-v0-core.c11 #include "dw-edma-core.h"
12 #include "dw-hdma-v0-core.h"
13 #include "dw-hdma-v0-regs.h"
14 #include "dw-hdma-v0-debugfs.h"
26 static inline struct dw_hdma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) in __dw_regs() argument
28 return dw->chip->reg_base; in __dw_regs()
32 __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) in __dw_ch_regs() argument
35 return &(__dw_regs(dw)->ch[ch].wr); in __dw_ch_regs()
37 return &(__dw_regs(dw)->ch[ch].rd); in __dw_ch_regs()
40 #define SET_CH_32(dw, dir, ch, name, value) \ argument
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H A Ddw-edma-core.c20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
22 #include "dw-hdma-v0-core.h"
35 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
67 struct dw_edma_chip *chip = desc->chan->dw->chip; in dw_edma_alloc_chunk()
176 struct dw_edma *dw = chan->dw; in dw_edma_start_transfer() local
194 dw_edma_core_start(dw, child, !desc->xfer_sz); in dw_edma_start_transfer()
209 if (chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) { in dw_edma_device_caps()
378 * If eDMA is embedded into the DW PCIe RP/EP and controlled from the in dw_edma_device_transfer()
393 if (chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) { in dw_edma_device_transfer()
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H A Ddw-edma-core.h76 struct dw_edma *dw; member
95 struct dw_edma *dw; member
121 void (*off)(struct dw_edma *dw);
122 u16 (*ch_count)(struct dw_edma *dw, enum dw_edma_dir dir);
128 void (*debugfs_on)(struct dw_edma *dw);
167 void dw_edma_core_off(struct dw_edma *dw) in dw_edma_core_off() argument
169 dw->core->off(dw); in dw_edma_core_off()
173 u16 dw_edma_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir) in dw_edma_core_ch_count() argument
175 return dw->core->ch_count(dw, dir); in dw_edma_core_ch_count()
181 return chan->dw->core->ch_status(chan); in dw_edma_core_ch_status()
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H A DMakefile3 obj-$(CONFIG_DW_EDMA) += dw-edma.o
4 dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o \
5 dw-hdma-v0-debugfs.o
6 dw-edma-objs := dw-edma-core.o \
7 dw-edma-v0-core.o \
8 dw-hdma-v0-core.o $(dw-edma-y)
9 obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi-ahb-audio.c22 #include "dw-hdmi-audio.h"
24 #define DRIVER_NAME "dw-hdmi-ahb-audio"
154 static void dw_hdmi_reformat_iec958(struct snd_dw_hdmi *dw, in dw_hdmi_reformat_iec958() argument
157 u32 *src = dw->buf_src + offset; in dw_hdmi_reformat_iec958()
158 u32 *dst = dw->buf_dst + offset; in dw_hdmi_reformat_iec958()
159 u32 *end = dw->buf_src + offset + bytes; in dw_hdmi_reformat_iec958()
182 static void dw_hdmi_reformat_s24(struct snd_dw_hdmi *dw, in dw_hdmi_reformat_s24() argument
185 u32 *src = dw->buf_src + offset; in dw_hdmi_reformat_s24()
186 u32 *dst = dw->buf_dst + offset; in dw_hdmi_reformat_s24()
187 u32 *end = dw->buf_src + offset + bytes; in dw_hdmi_reformat_s24()
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H A Ddw-hdmi-gp-audio.c3 * dw-hdmi-gp-audio.c
26 #include "dw-hdmi-audio.h"
28 #define DRIVER_NAME "dw-hdmi-gp-audio"
79 struct snd_dw_hdmi *dw = dev_get_drvdata(dev); in audio_hw_params() local
82 dw_hdmi_set_sample_rate(dw->data.hdmi, params->sample_rate); in audio_hw_params()
86 dw_hdmi_set_channel_count(dw->data.hdmi, params->channels); in audio_hw_params()
87 dw_hdmi_set_channel_allocation(dw->data.hdmi, ca); in audio_hw_params()
89 dw_hdmi_set_sample_non_pcm(dw->data.hdmi, in audio_hw_params()
91 dw_hdmi_set_sample_width(dw->data.hdmi, params->sample_width); in audio_hw_params()
103 struct snd_dw_hdmi *dw = dev_get_drvdata(dev); in audio_mute_stream() local
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/linux/drivers/dma/dw/
H A Dcore.c80 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_get() local
84 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); in dwc_desc_get()
99 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_put() local
107 dma_pool_free(dw->desc_pool, child, child->txd.phys); in dwc_desc_put()
111 dma_pool_free(dw->desc_pool, desc, desc->txd.phys); in dwc_desc_put()
117 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_initialize() local
119 dw->initialize_chan(dwc); in dwc_initialize()
122 channel_set_bit(dw, MASK.XFER, dwc->mask); in dwc_initialize()
123 channel_set_bit(dw, MASK.ERROR, dwc->mask); in dwc_initialize()
139 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) in dwc_chan_disable() argument
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H A Ddw.c16 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dw_dma_initialize_chan() local
23 cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl); in dw_dma_initialize_chan()
100 static void dw_dma_set_device_name(struct dw_dma *dw, int id) in dw_dma_set_device_name() argument
102 snprintf(dw->name, sizeof(dw->name), "dw:dmac%d", id); in dw_dma_set_device_name()
105 static void dw_dma_disable(struct dw_dma *dw) in dw_dma_disable() argument
107 do_dw_dma_off(dw); in dw_dma_disable()
110 static void dw_dma_enable(struct dw_dma *dw) in dw_dma_enable() argument
112 do_dw_dma_on(dw); in dw_dma_enable()
117 struct dw_dma *dw; in dw_dma_probe() local
119 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); in dw_dma_probe()
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H A Didma32.c48 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in idma32_initialize_chan_xbar() local
49 void __iomem *misc = __dw_regs(dw); in idma32_initialize_chan_xbar()
221 static void idma32_set_device_name(struct dw_dma *dw, int id) in idma32_set_device_name() argument
223 snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", id); in idma32_set_device_name()
232 static void idma32_fifo_partition(struct dw_dma *dw) in idma32_fifo_partition() argument
245 idma32_writeq(dw, FIFO_PARTITION1, fifo_partition); in idma32_fifo_partition()
246 idma32_writeq(dw, FIFO_PARTITION0, fifo_partition); in idma32_fifo_partition()
249 static void idma32_disable(struct dw_dma *dw) in idma32_disable() argument
251 do_dw_dma_off(dw); in idma32_disable()
252 idma32_fifo_partition(dw); in idma32_disable()
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H A Dinternal.h11 #include <linux/dma/dw.h>
18 void do_dw_dma_on(struct dw_dma *dw);
19 void do_dw_dma_off(struct dw_dma *dw);
27 void dw_dma_acpi_controller_register(struct dw_dma *dw);
28 void dw_dma_acpi_controller_free(struct dw_dma *dw);
30 static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {} in dw_dma_acpi_controller_register() argument
31 static inline void dw_dma_acpi_controller_free(struct dw_dma *dw) {} in dw_dma_acpi_controller_free() argument
38 void dw_dma_of_controller_register(struct dw_dma *dw);
39 void dw_dma_of_controller_free(struct dw_dma *dw);
45 static inline void dw_dma_of_controller_register(struct dw_dma *dw) {} in dw_dma_of_controller_register() argument
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/linux/drivers/pci/controller/dwc/
H A Dpcie-rcar-gen4.c81 struct dw_pcie dw; member
87 #define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
90 static bool rcar_gen4_pcie_link_up(struct dw_pcie *dw) in rcar_gen4_pcie_link_up() argument
92 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); in rcar_gen4_pcie_link_up()
105 static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw) in rcar_gen4_pcie_speed_change() argument
110 val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); in rcar_gen4_pcie_speed_change()
112 dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val); in rcar_gen4_pcie_speed_change()
114 val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); in rcar_gen4_pcie_speed_change()
116 dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val); in rcar_gen4_pcie_speed_change()
119 val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); in rcar_gen4_pcie_speed_change()
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/linux/include/uapi/scsi/
H A Dscsi_bsg_ufs.h18 /* uic commands are 4DW long, per UFSHCI V2.1 paragraph 5.6.1 */
41 * @dword_0: UPIU header DW-0
42 * @dword_1: UPIU header DW-1
43 * @dword_2: UPIU header DW-2
105 * @value: Attribute value to be written DW-5
106 * @reserved: spec reserved DW-6,7
129 * @osf6: spec field DW 8,9
130 * @osf7: spec field DW 10,11
148 * @exp_data_transfer_len: Data Transfer Length DW-3
149 * @cdb: Command Descriptor Block CDB DW-4 to DW-7
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/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2cd.dtsi175 compatible = "snps,dw-apb-gpio";
181 compatible = "snps,dw-apb-gpio-port";
193 compatible = "snps,dw-apb-gpio";
199 compatible = "snps,dw-apb-gpio-port";
211 compatible = "snps,dw-apb-gpio";
217 compatible = "snps,dw-apb-gpio-port";
229 compatible = "snps,dw-apb-gpio";
235 compatible = "snps,dw-apb-gpio-port";
267 compatible = "snps,dw-apb-ssi";
277 compatible = "snps,dw-wdt";
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H A Dberlin2.dtsi185 compatible = "snps,dw-apb-gpio";
191 compatible = "snps,dw-apb-gpio-port";
203 compatible = "snps,dw-apb-gpio";
209 compatible = "snps,dw-apb-gpio-port";
221 compatible = "snps,dw-apb-gpio";
227 compatible = "snps,dw-apb-gpio-port";
239 compatible = "snps,dw-apb-gpio";
245 compatible = "snps,dw-apb-gpio-port";
257 compatible = "snps,dw-apb-timer";
266 compatible = "snps,dw-apb-timer";
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H A Dberlin2q.dtsi246 compatible = "snps,dw-apb-gpio";
252 compatible = "snps,dw-apb-gpio-port";
264 compatible = "snps,dw-apb-gpio";
270 compatible = "snps,dw-apb-gpio-port";
282 compatible = "snps,dw-apb-gpio";
288 compatible = "snps,dw-apb-gpio-port";
300 compatible = "snps,dw-apb-gpio";
306 compatible = "snps,dw-apb-gpio-port";
342 compatible = "snps,dw-apb-timer";
350 compatible = "snps,dw-apb-timer";
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/linux/Documentation/devicetree/bindings/mmc/
H A Dk3-dw-mshc.txt4 Read synopsys-dw-mshc.txt for more details
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
30 compatible = "hisilicon,hi4511-dw-mshc";
55 compatible = "hisilicon,hi6220-dw-mshc";
/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml4 $id: http://devicetree.org/schemas/watchdog/snps,dw-wdt.yaml#
18 - const: snps,dw-wdt
37 - const: snps,dw-wdt
43 description: DW Watchdog pre-timeout interrupt
59 description: Phandle to the DW Watchdog reset lane
65 DW APB Watchdog custom timer intervals - Timeout Period ranges (TOPs).
69 the timer expiration intervals supported by the DW APB Watchdog. Note
70 DW APB Watchdog IP-core might be synthesized with fixed TOP values,
89 compatible = "snps,dw-wdt";
98 compatible = "snps,dw-wdt";
/linux/arch/arm64/boot/dts/synaptics/
H A Dberlin4ct.dtsi136 compatible = "snps,dw-apb-gpio";
142 compatible = "snps,dw-apb-gpio-port";
154 compatible = "snps,dw-apb-gpio";
160 compatible = "snps,dw-apb-gpio-port";
172 compatible = "snps,dw-apb-gpio";
178 compatible = "snps,dw-apb-gpio-port";
190 compatible = "snps,dw-apb-gpio";
196 compatible = "snps,dw-apb-gpio-port";
208 compatible = "snps,dw-apb-ictl";
235 compatible = "snps,dw-apb-ictl";
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/linux/Documentation/devicetree/bindings/net/pcs/
H A Dsnps,dw-xpcs.yaml4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
29 const: snps,dw-xpcs
31 const: snps,dw-xpcs-gen1-3g
33 const: snps,dw-xpcs-gen2-3g
35 const: snps,dw-xpcs-gen2-6g
37 const: snps,dw-xpcs-gen4-3g
39 const: snps,dw-xpcs-gen4-6g
41 const: snps,dw-xpcs-gen5-10g
43 const: snps,dw-xpcs-gen5-12g
49 of the MDIO bus device. If DW XPCS CSRs space is accessed over the
[all …]
/linux/arch/arc/boot/dts/
H A Daxs10x_mb.dtsi55 * DW sdio controller has external ciu clock divider
103 * According to DW Mobile Storage databook it is required
112 * "altr,socfpga-dw-mshc".
116 * "snps,dw-mshc" should be enough for all users of DW MMC once
121 compatible = "altr,socfpga-dw-mshc";
132 compatible = "snps,dw-apb-uart";
142 compatible = "snps,dw-apb-uart";
153 compatible = "snps,dw-apb-uart";
244 compatible = "snps,dw-apb-gpio";
250 compatible = "snps,dw-apb-gpio-port";
[all …]
/linux/include/ufs/
H A Dufshci.h470 * @addr: Physical address; DW-0 and DW-1.
471 * @reserved: Reserved for future use DW-2
472 * @size: size of physical segment DW-3
534 * @header: UTRD header DW-0 to DW-3
535 * @command_desc_base_addr: UCD base address DW 4-5
536 * @response_upiu_length: response UPIU length DW-6
537 * @response_upiu_offset: response UPIU offset DW-6
538 * @prd_table_length: Physical region descriptor length DW-7
539 * @prd_table_offset: Physical region descriptor offset DW-7
543 /* DW 0-3 */
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/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dpio_phy_regs.h11 #define _VLV_CMN(dw) (0x8100 + (dw) * 4) argument
12 #define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4) argument
13 #define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */ argument
14 #define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4) argument
15 #define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */ argument
16 #define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4) argument
17 #define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4) argument
18 #define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4) argument
19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
20 #define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4) argument
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