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/linux/drivers/gpu/drm/bridge/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 Simple transparent bridge that is used by several non-DRM drivers to
36 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
43 ICN6211 is MIPI-DSI/RGB Converter bridge from chipone.
45 It has a flexible configuration of MIPI DSI signal input
67 ChromeOS EC ANX7688 is an ultra-low power
68 4K Ultra-HD (4096x2160p60) mobile HD transmitter
70 2.0 to DisplayPort 1.3 Ultra-HD. It is connected
71 to the ChromeOS Embedded Controller.
77 Driver for display connectors with support for DDC and hot-plug
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H A Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
116 /* fudge factor required to account for 8b/10b encoding */
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
140 * @dev: Pointer to the top level (i2c) device.
145 * @host_node: Remote DSI node.
146 * @dsi: Our MIPI DSI source.
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H A Dparade-ps8640.c1 // SPDX-License-Identifier: GPL-2.0-only
74 * page[3]: for DSI Link Control1
77 * page[6]: for DSI Link Control2
101 struct mipi_dsi_device *dsi; member
160 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; in _ps8640_wait_hpd_asserted()
167 * actually connected to GPIO9). in _ps8640_wait_hpd_asserted()
175 * time (maybe talking to the panel) and we don't want to interrupt it. in _ps8640_wait_hpd_asserted()
181 if (!ret && ps_bridge->need_post_hpd_delay) { in _ps8640_wait_hpd_asserted()
182 ps_bridge->need_post_hpd_delay = false; in _ps8640_wait_hpd_asserted()
192 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; in ps8640_wait_hpd_asserted()
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H A Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
76 /* DSI layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
78 #define DSI_BUSYDSI 0x0208 /* DSI busy status */
82 /* Lane enable PPI and DSI register bits */
89 #define DSI_LANESTATUS0 0x0214 /* DSI lane status 0 */
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dtoshiba,tc358767.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358767/TC358867/TC9595 DSI/DPI/eDP bridge
10 - Andrey Gusakov <andrey.gusakov@cogentembedded.com>
14 converts DSI/DPI to eDP/DP .
19 - items:
20 - enum:
21 - toshiba,tc358867
22 - toshiba,tc9595
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H A Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPI DSI to eDP Video Format Converter
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
14 mobile devices with embedded panel resolutions up to 2048 x 1536. The
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
17 device outputs eDP v1.4, one or two lanes, at a link rate of up to
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H A Dti,sn65dsi86.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI86 DSI to eDP bridge chip
10 - Douglas Anderson <dianders@chromium.org>
13 The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
23 enable-gpios:
27 suspend-gpios:
31 no-hpd:
34 Set if the HPD line on the bridge isn't hooked up to anything or is
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/linux/Documentation/gpu/
H A Dtegra.rst7 buffer provided directly by the CPU, to its clients via channels. Software,
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
22 outputs, such as RGB, HDMI, DSI, and DisplayPort.
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
30 The various host1x clients need to be bound together into a logical device in
31 order to expose their functionality to users. The infrastructure that supports
35 tree for matching device nodes, adding the required clients to a list. Drivers
37 to the logical host1x device.
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_bios.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
50 * configuration information to the driver that is not discoverable or available
51 * through other means. The configuration is mostly related to display
60 * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of
80 /* Get BDB block size given a pointer to Block ID. */
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H A Dintel_display_types.h3 * Copyright (c) 2007-2008 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
67 /* these are outputs from the chip - integrated only
85 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
100 * The remap information used in the remapped and rotated views to
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H A Dintel_display_power.h1 /* SPDX-License-Identifier: MIT */
24 * consecutive, so that the pipe,transcoder,port -> power domain macros
45 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
168 for_each_if(test_bit((__domain), (__mask)->bits))
208 __intel_display_power_put_async(i915, domain, wakeref, -1); in intel_display_power_put_async()
236 __intel_display_power_put_async(i915, domain, INTEL_WAKEREF_DEF, -1); in intel_display_power_put_async()
268 intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask); in intel_display_power_put_all_in_set()
285 * FIXME: We should probably switch this to a 0-based scheme to be consistent
H A Dintel_vdsc.c1 // SPDX-License-Identifier: MIT
25 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_source_support()
26 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_dsc_source_support()
27 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_source_support()
40 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in is_pipe_dsc()
51 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); in is_pipe_dsc()
60 int bpc = vdsc_cfg->bits_per_component; in intel_vdsc_set_min_max_qp()
63 vdsc_cfg->rc_range_params[buf].range_min_qp = in intel_vdsc_set_min_max_qp()
64 intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420); in intel_vdsc_set_min_max_qp()
65 vdsc_cfg->rc_range_params[buf].range_max_qp = in intel_vdsc_set_min_max_qp()
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H A Dintel_display.h2 * Copyright © 2006-2019 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
82 return "EDP"; in transcoder_name()
84 return "DSI A"; in transcoder_name()
86 return "DSI C"; in transcoder_name()
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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sc7280-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
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H A Dqcom,mdp5.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
15 - Rob Clark <robdclark@gmail.com>
20 - const: qcom,mdp5
22 - items:
23 - enum:
24 - qcom,apq8084-mdp5
25 - qcom,msm8226-mdp5
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/linux/drivers/gpu/drm/panel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 Say Y here to enable support for the Asia Better Technology Ltd.
17 Y030XX067A 320x480 3.0" panel as found in the YLM RG-280M, RG-300
18 and RG-99 handheld gaming consoles.
26 This driver supports the ARM Versatile panels connected to ARM
36 Say Y here if you want to enable support for the ASUS TMP5P5
45 Say Y here to enable support for the AUO A030JTN01 320x480 3.0" panel
46 as found in the YLM RS-97 handheld gaming console.
49 tristate "Boe BF060Y8M-AJ0 panel"
54 Say Y here if you want to enable support for Boe BF060Y8M-AJ0
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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <jonathan@marek.ca>
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
24 - qcom,sc8180x-dispcc
25 - qcom,sm8150-dispcc
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/linux/drivers/gpu/drm/msm/
H A DNOTES5 + MDP3 - ?? seems to be what is on geeksphone peak device
6 + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
7 + MDP5 - snapdragon 800
10 maps to which part #)
12 Plus a handful of blocks around them for HDMI/DSI/etc output.
18 But, HDMI/DSI/etc blocks seem like they can be shared across multiple
19 display controller blocks. And I for sure don't want to have to deal
20 with N different kms devices from xf86-video-freedreno. Plus, it
21 seems like we can do some clever tricks like use GPU to trigger
23 up gpu cmdstream to update scanout and write FLUSH register after).
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/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
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/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 series of SoCs which transfers the image data from a video memory buffer to
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,rk3566-vop
22 - rockchip,rk3568-vop
23 - rockchip,rk3588-vop
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/media-bus-format.h>
48 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector()
50 if (connector->encoder == encoder) { in sun4i_tcon_get_connector()
66 return -EINVAL; in sun4i_tcon_get_pixel_depth()
68 info = &connector->display_info; in sun4i_tcon_get_pixel_depth()
69 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth()
70 return -EINVAL; in sun4i_tcon_get_pixel_depth()
72 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
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/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_encoder.c1 // SPDX-License-Identifier: GPL-2.0-only
15 struct msm_drm_private *priv = encoder->dev->dev_private; in get_kms()
16 return to_mdp5_kms(to_mdp_kms(priv->kms)); in get_kms()
25 struct drm_device *dev = encoder->dev; in mdp5_vid_encoder_mode_set()
27 int intf = mdp5_encoder->intf->num; in mdp5_vid_encoder_mode_set()
40 /* DSI controller cannot handle active-low sync signals. */ in mdp5_vid_encoder_mode_set()
41 if (mdp5_encoder->intf->type != INTF_DSI) { in mdp5_vid_encoder_mode_set()
42 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in mdp5_vid_encoder_mode_set()
44 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in mdp5_vid_encoder_mode_set()
47 /* probably need to get DATA_EN polarity from panel.. */ in mdp5_vid_encoder_mode_set()
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H A Dmdp5_kms.c1 // SPDX-License-Identifier: GPL-2.0-only
25 struct device *dev = &mdp5_kms->pdev->dev; in mdp5_hw_init()
47 * Not setting these does not seem to cause any problem. But in mdp5_hw_init()
50 * setting the golden registers, then perhaps we don't need to in mdp5_hw_init()
54 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); in mdp5_hw_init()
56 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); in mdp5_hw_init()
58 mdp5_ctlm_hw_reset(mdp5_kms->ctlm); in mdp5_hw_init()
75 return to_mdp5_global_state(mdp5_kms->glob_state.state); in mdp5_get_existing_global_state()
84 struct msm_drm_private *priv = s->dev->dev_private; in mdp5_get_global_state()
85 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); in mdp5_get_global_state()
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
43 * internal firmware(OCM), to avoid the race condition, AP should access
50 struct device *dev = &client->dev; in i2c_access_workaround()
53 if (client == ctx->last_client) in i2c_access_workaround()
56 ctx->last_client = client; in i2c_access_workaround()
58 if (client == ctx->i2c.tcpc_client) in i2c_access_workaround()
60 else if (client == ctx->i2c.tx_p0_client) in i2c_access_workaround()
62 else if (client == ctx->i2c.tx_p1_client) in i2c_access_workaround()
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/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
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