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/linux/drivers/gpu/drm/bridge/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 Simple transparent bridge that is used by several non-DRM drivers to
36 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
43 ICN6211 is MIPI-DSI/RGB Converter bridge from chipone.
45 It has a flexible configuration of MIPI DSI signal input
67 ChromeOS EC ANX7688 is an ultra-low power
68 4K Ultra-HD (4096x2160p60) mobile HD transmitter
70 2.0 to DisplayPort 1.3 Ultra-HD. It is connected
71 to the ChromeOS Embedded Controller.
77 Driver for display connectors with support for DDC and hot-plug
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H A Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
116 /* fudge factor required to account for 8b/10b encoding */
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
140 * @dev: Pointer to the top level (i2c) device.
145 * @host_node: Remote DSI node.
146 * @dsi: Our MIPI DSI source.
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H A Dparade-ps8640.c1 // SPDX-License-Identifier: GPL-2.0-only
74 * page[3]: for DSI Link Control1
77 * page[6]: for DSI Link Control2
101 struct mipi_dsi_device *dsi; member
160 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; in _ps8640_wait_hpd_asserted()
167 * actually connected to GPIO9). in _ps8640_wait_hpd_asserted()
175 * time (maybe talking to the panel) and we don't want to interrupt it. in _ps8640_wait_hpd_asserted()
181 if (!ret && ps_bridge->need_post_hpd_delay) { in _ps8640_wait_hpd_asserted()
182 ps_bridge->need_post_hpd_delay = false; in _ps8640_wait_hpd_asserted()
192 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; in ps8640_wait_hpd_asserted()
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/linux/Documentation/gpu/
H A Dtegra.rst7 buffer provided directly by the CPU, to its clients via channels. Software,
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
22 outputs, such as RGB, HDMI, DSI, and DisplayPort.
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
30 The various host1x clients need to be bound together into a logical device in
31 order to expose their functionality to users. The infrastructure that supports
35 tree for matching device nodes, adding the required clients to a list. Drivers
37 to the logical host1x device.
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPI DSI to eDP Video Format Converter
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
14 mobile devices with embedded panel resolutions up to 2048 x 1536. The
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
17 device outputs eDP v1.4, one or two lanes, at a link rate of up to
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H A Dti,sn65dsi86.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI86 DSI to eDP bridge chip
10 - Douglas Anderson <dianders@chromium.org>
13 The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
23 enable-gpios:
27 suspend-gpios:
31 no-hpd:
34 Set if the HPD line on the bridge isn't hooked up to anything or is
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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sc7280-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
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H A Dqcom,mdp5.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
15 - Rob Clark <robdclark@gmail.com>
20 - const: qcom,mdp5
22 - items:
23 - enum:
24 - qcom,apq8084-mdp5
25 - qcom,msm8226-mdp5
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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <jonathan@marek.ca>
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
24 - qcom,sc8180x-dispcc
25 - qcom,sm8150-dispcc
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/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DSI Controller
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
15 The MediaTek DSI function block is a sink of the display subsystem and can
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
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/linux/drivers/gpu/drm/msm/
H A DNOTES5 + MDP3 - ?? seems to be what is on geeksphone peak device
6 + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
7 + MDP5 - snapdragon 800
10 maps to which part #)
12 Plus a handful of blocks around them for HDMI/DSI/etc output.
18 But, HDMI/DSI/etc blocks seem like they can be shared across multiple
19 display controller blocks. And I for sure don't want to have to deal
20 with N different kms devices from xf86-video-freedreno. Plus, it
21 seems like we can do some clever tricks like use GPU to trigger
23 up gpu cmdstream to update scanout and write FLUSH register after).
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H A Dmsm_mdss.c2 * SPDX-License-Identifier: GPL-2.0
58 path0 = devm_of_icc_get(dev, "mdp0-mem"); in msm_mdss_parse_data_bus_icc_path()
62 msm_mdss->mdp_path[0] = path0; in msm_mdss_parse_data_bus_icc_path()
63 msm_mdss->num_mdp_paths = 1; in msm_mdss_parse_data_bus_icc_path()
65 path1 = devm_of_icc_get(dev, "mdp1-mem"); in msm_mdss_parse_data_bus_icc_path()
67 msm_mdss->mdp_path[1] = path1; in msm_mdss_parse_data_bus_icc_path()
68 msm_mdss->num_mdp_paths++; in msm_mdss_parse_data_bus_icc_path()
71 reg_bus_path = of_icc_get(dev, "cpu-cfg"); in msm_mdss_parse_data_bus_icc_path()
73 msm_mdss->reg_bus_path = reg_bus_path; in msm_mdss_parse_data_bus_icc_path()
86 interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS); in msm_mdss_irq()
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/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_types.h3 * Copyright (c) 2007-2008 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
48 #include <media/cec-notifier.h>
71 /* these are outputs from the chip - integrated only
89 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
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H A Dintel_display_power.h1 /* SPDX-License-Identifier: MIT */
23 * consecutive, so that the pipe,transcoder,port -> power domain macros
44 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
167 for_each_if(test_bit((__domain), (__mask)->bits))
207 __intel_display_power_put_async(i915, domain, wakeref, -1);
235 __intel_display_power_put_async(i915, domain, -1, -1);
244 __intel_display_power_put_async(i915, domain, -
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H A Dintel_psr.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
49 * Since Haswell Display controller supports Panel Self-Refresh on display
50 * panels witch have a remote frame buffer (RFB) implemented according to PSR
51 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
53 * request to DDR memory completely as long as the frame buffer for that
[all …]
H A Dintel_ddi.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
99 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
101 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
119 * DP/eDP/FDI use cases.
124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
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/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 series of SoCs which transfers the image data from a video memory buffer to
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,rk3566-vop
22 - rockchip,rk3568-vop
23 - rockchip,rk3588-vop
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/linux/drivers/gpu/drm/
H A Ddrm_modeset_helper.c4 * Permission to use, copy, modify, distribute, and sell this software and its
9 * publicity pertaining to distribution of the software without specific,
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
35 * This helper library contains various one-off functions which don't really fit
40 * drm_helper_move_panel_connectors_to_head() - move panels to the front in the
42 * @dev: drm device to operate on
45 * display, where it's supposed to display e.g. the login screen. For
46 * laptops, this should be the main panel. Use this function to sort all
47 * (eDP/LVDS/DSI) panels to the front of the connector list, instead of
48 * painstakingly trying to initialize them in the right order.
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/media-bus-format.h>
48 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector()
50 if (connector->encoder == encoder) { in sun4i_tcon_get_connector()
66 return -EINVAL; in sun4i_tcon_get_pixel_depth()
68 info = &connector->display_info; in sun4i_tcon_get_pixel_depth()
69 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth()
70 return -EINVAL; in sun4i_tcon_get_pixel_depth()
72 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
[all …]
/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_encoder.c1 // SPDX-License-Identifier: GPL-2.0-only
15 struct msm_drm_private *priv = encoder->dev->dev_private; in get_kms()
16 return to_mdp5_kms(to_mdp_kms(priv->kms)); in get_kms()
25 struct drm_device *dev = encoder->dev; in mdp5_vid_encoder_mode_set()
27 int intf = mdp5_encoder->intf->num; in mdp5_vid_encoder_mode_set()
40 /* DSI controller cannot handle active-low sync signals. */ in mdp5_vid_encoder_mode_set()
41 if (mdp5_encoder->intf->type != INTF_DSI) { in mdp5_vid_encoder_mode_set()
42 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in mdp5_vid_encoder_mode_set()
44 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in mdp5_vid_encoder_mode_set()
47 /* probably need to get DATA_EN polarity from panel.. */ in mdp5_vid_encoder_mode_set()
[all …]
H A Dmdp5_kms.c1 // SPDX-License-Identifier: GPL-2.0-only
25 struct device *dev = &mdp5_kms->pdev->dev; in mdp5_hw_init()
47 * Not setting these does not seem to cause any problem. But in mdp5_hw_init()
50 * setting the golden registers, then perhaps we don't need to in mdp5_hw_init()
54 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); in mdp5_hw_init()
56 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); in mdp5_hw_init()
58 mdp5_ctlm_hw_reset(mdp5_kms->ctlm); in mdp5_hw_init()
75 return to_mdp5_global_state(mdp5_kms->glob_state.state); in mdp5_get_existing_global_state()
84 struct msm_drm_private *priv = s->dev->dev_private; in mdp5_get_global_state()
85 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); in mdp5_get_global_state()
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/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder_phys_vid.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
18 (e) && (e)->parent ? \
19 (e)->parent->base.id : -1, \
20 (e) && (e)->hw_intf ? \
21 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
24 (e) && (e)->parent ? \
25 (e)->parent->base.id : -1, \
26 (e) && (e)->hw_intf ? \
27 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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