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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Svyatoslav Ryhel <clamor95@gmail.com>
15 - nvidia,tegra20-csi
16 - nvidia,tegra30-csi
24 - description: module clock
25 - description: PAD A clock
26 - description: PAD B clock
[all …]
H A Dnvidia,tegra210-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^csi@[0-9a-f]+$"
19 - nvidia,tegra210-csi
26 - description: module clock
27 - description: A/B lanes clock
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
[all …]
H A Dlontium,lt9211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.
10 - Marek Vasut <marex@denx.de>
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
19 - lontium,lt9211
27 reset-gpios:
31 vccio-supply:
[all …]
H A Dti,dlpc3433.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI DLPC3433 MIPI DSI to DMD bridge
10 - Jagan Teki <jagan@amarulasolutions.com>
11 - Christopher Vollo <chris@renewoutreach.org>
14 TI DLPC3433 is a MIPI DSI based display controller bridge
17 It has a flexible configuration of MIPI DSI and DPI signal
30 - 0x1b
31 - 0x1d
[all …]
/linux/Documentation/devicetree/bindings/display/panel/
H A Dhimax,hx83112a.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Himax HX83112A-based DSI display panels
10 - Luca Weiss <luca.weiss@fairphone.com>
13 The Himax HX83112A is a generic DSI Panel IC used to control
17 - $ref: panel-common.yaml#
22 const: djn,9a-3r063-1102b
27 vdd1-supply:
30 vsn-supply:
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9211.c1 // SPDX-License-Identifier: GPL-2.0
6 * 2xDSI/2xLVDS/1xDPI -> 2xDSI/2xLVDS/1xDPI
8 * 1xDSI -> 1xLVDS
17 #include <linux/media-bus-format.h>
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
47 struct mipi_dsi_device *dsi; member
107 return drm_bridge_attach(encoder, ctx->panel_bridge, in lt9211_attach()
108 &ctx->bridge, flags); in lt9211_attach()
117 ret = regmap_bulk_read(ctx->regmap, REG_CHIPID0, chipid, 3); in lt9211_read_chipid()
119 dev_err(ctx->dev, "Failed to read Chip ID: %d\n", ret); in lt9211_read_chipid()
[all …]
H A Dlontium-lt8912b.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/media-bus-format.h>
40 struct mipi_dsi_device *dsi; member
89 return regmap_multi_reg_write(lt->regmap[I2C_MAIN], seq, ARRAY_SIZE(seq)); in lt8912_write_init_config()
102 return regmap_multi_reg_write(lt->regmap[I2C_CEC_DSI], seq, ARRAY_SIZE(seq)); in lt8912_write_mipi_basic_config()
155 return regmap_multi_reg_write(lt->regmap[I2C_CEC_DSI], seq, ARRAY_SIZE(seq)); in lt8912_write_dds_config()
162 ret = regmap_write(lt->regmap[I2C_MAIN], 0x03, 0x7f); in lt8912_write_rxlogicres_config()
164 ret |= regmap_write(lt->regmap[I2C_MAIN], 0x03, 0xff); in lt8912_write_rxlogicres_config()
180 {0x52, 0x04}, // loopdiv=0, use second-order PLL in lt8912_write_lvds_config()
200 return regmap_multi_reg_write(lt->regmap[I2C_MAIN], seq, ARRAY_SIZE(seq)); in lt8912_write_lvds_config()
[all …]
H A Dlontium-lt9611.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2019-2020. Linaro Limited.
10 #include <linux/media-bus-format.h>
17 #include <sound/hdmi-codec.h>
100 { 0x8111, 0x40 }, /* port B rx current */ in lt9611_mipi_input_analog()
101 { 0x8115, 0xfe }, /* port B ldo voltage set */ in lt9611_mipi_input_analog()
102 { 0x8116, 0xbf }, /* enable port B lprx */ in lt9611_mipi_input_analog()
104 { 0x811c, 0x03 }, /* PortA clk lane no-LP mode */ in lt9611_mipi_input_analog()
105 { 0x8120, 0x03 }, /* PortB clk lane with-LP mode */ in lt9611_mipi_input_analog()
108 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_analog()
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
228 static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b) in bridge_to_dsi() argument
230 return container_of(b, struct mtk_dsi, bridge); in bridge_to_dsi()
238 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) in mtk_dsi_mask() argument
240 u32 temp = readl(dsi->regs + offset); in mtk_dsi_mask()
242 writel((temp & ~mask) | (data & mask), dsi->regs + offset); in mtk_dsi_mask()
245 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) in mtk_dsi_phy_timconfig() argument
248 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ); in mtk_dsi_phy_timconfig()
249 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig()
251 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; in mtk_dsi_phy_timconfig()
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_drv.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 * DOC: ST-Ericsson MCDE Driver
11 * The MCDE (short for multi-channel display engine) is a graphics
15 * ST-Ericsson U8500 where is was used for mass-market deployments
18 * It can do 1080p30 on SDTV CCIR656, DPI-2, DBI-2 or DSI for
25 * Memory -> Overlay -> Channel -> FIFO -> 8 formatters -> DSI/DPI
26 * External 0..5 0..3 A,B, 6 x DSI bridge
29 * FIFOs A and B are for LCD and HDMI while FIFO CO/C1 are for
31 * 6 of the formatters are for DSI, 3 pairs for VID/CMD respectively.
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-raspberrypi-touchscreen.c2 * Copyright © 2016-2017 Broadcom
8 * Portions of this file (derived from panel-simple.c) are:
25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
36 * TC358762XBG DSI-DPI bridge, and an I2C-connected Atmel ATTINY88-MUR
40 * This driver controls the TC358762 and ATTINY88, presenting a DSI
47 #include <linux/media-bus-format.h>
58 #define RPI_DSI_DRIVER_NAME "rpi-ts-dsi"
83 /* DSI D-PHY Layer Registers */
94 /* DSI PPI Layer Registers */
118 /* DSI Protocol Layer Registers */
[all …]
/linux/Documentation/gpu/
H A Dtegra.rst11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
22 outputs, such as RGB, HDMI, DSI, and DisplayPort.
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
52 .. kernel-doc:: drivers/gpu/host1x/bus.c
56 --------------------------
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
50 struct device *dev = &client->dev; in i2c_access_workaround()
53 if (client == ctx->last_client) in i2c_access_workaround()
56 ctx->last_client = client; in i2c_access_workaround()
58 if (client == ctx->i2c.tcpc_client) in i2c_access_workaround()
60 else if (client == ctx->i2c.tx_p0_client) in i2c_access_workaround()
62 else if (client == ctx->i2c.tx_p1_client) in i2c_access_workaround()
64 else if (client == ctx->i2c.rx_p0_client) in i2c_access_workaround()
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/video/omap2/dss/dsi.c
9 #define DSS_SUBSYS_NAME "DSI"
47 /* DSI Protocol Engine */
213 /* DSI PLL HSDIV indices */
408 return to_platform_device(dssdev->dev); in dsi_get_dsidev_from_dssdev()
429 return out ? to_platform_device(out->dev) : NULL; in dsi_get_dsidev_from_id()
435 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); in dsi_write_reg() local
439 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
440 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp157f-dk2-scmi.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
7 #include "stm32mp15-scmi.dtsi"
10 reserved-memory {
13 no-map;
18 compatible = "arm,smc-wdt";
19 arm,smc-id = <0xbc000000>;
26 vdd-supply = <&scmi_vdd>;
27 vdda-supply = <&scmi_vdd>;
44 VL-supply = <&scmi_v3v3>;
[all …]
H A Dste-ab8505.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/ste-ab8500.h>
10 iio-hwmon {
11 compatible = "iio-hwmon";
12 io-channels = <&gpadc 0x02>, /* Battery temperature */
24 interrupt-parent = <&intc>;
26 interrupt-controller;
27 #interrupt-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
[all …]
H A Dste-ab8500.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/ste-ab8500.h>
10 iio-hwmon {
11 compatible = "iio-hwmon";
12 io-channels = <&gpadc 0x02>, /* Battery temperature */
27 interrupt-parent = <&intc>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
31 #address-cells = <1>;
32 #size-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779a0-falcon-csi-dsi.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Falcon CSI/DSI sub-board
8 #include <dt-bindings/media/video-interfaces.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
21 clock-lanes = <0>;
22 data-lanes = <1 2 3 4>;
23 remote-endpoint = <&max96712_out0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
[all …]
H A Dwhite-hawk-csi-dsi.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the White Hawk CSI/DSI sub-board
8 #include <dt-bindings/media/video-interfaces.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
21 bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
22 clock-lanes = <0>;
23 data-lanes = <1 2 3>;
24 line-orders = <MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC
27 remote-endpoint = <&max96712_out0>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2025 GOcontroll B.V.
7 #include <dt-bindings/gpio/gpio.h>
9 #include "imx8mp-pinfunc.h"
11 /dts-v1/;
15 model = "GOcontroll Moduline Display with BOE av123z7m-n17 display";
18 compatible = "boe,av123z7m-n17";
19 enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
20 pinctrl-0 = <&pinctrl_panel>;
21 pinctrl-names = "default";
[all …]
/linux/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
256 #define CFG_H_BACK_PORCH(b) ((b)<<16) argument
259 #define CFG_V_BACK_PORCH(b) ((b)<<16) argument
386 #define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */
388 #define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */
411 1. Smart Pannel 8-bit Bus Control Register.
685 /* FIXME - JUST GUESS */
[all …]
/linux/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c1 // SPDX-License-Identifier: GPL-2.0
22 #define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2) argument
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
42 if (pll->potential_fvco >= VCO_BAND_LOW && in dphy_calc_pll_param()
43 pll->potential_fvco <= VCO_BAND_HIGH) { in dphy_calc_pll_param()
44 pll->fvco = pll->potential_fvco; in dphy_calc_pll_param()
45 pll->out_sel = BIT(i); in dphy_calc_pll_param()
48 pll->potential_fvco <<= 1; in dphy_calc_pll_param()
50 if (pll->fvco == 0) in dphy_calc_pll_param()
[all …]
/linux/drivers/gpu/drm/gma500/
H A Doaktrail.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2007-2011, Intel Corporation.
78 /* Bit 0, Frequency, 15 bits,0 - 32767Hz */
84 /* 0: Type-1, */
85 /* 1: Type-2, */
86 /* 2: Type-3, */
87 /* 3: Type-4 */
93 /* Bit 6, Reserved, 2 bits, 00b */
94 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
95 /* Bit 14, Reserved, 2 bits, 00b */
[all …]
/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
10 #include <dt-bindings/phy/phy.h>
15 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
22 v = (tmax - tmin) * percent; in linear_inter()
25 return max_t(s32, min_result, v - 1); in linear_inter()
37 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
38 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
48 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
49 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
[all …]

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