| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hw_dsc.h | 19 * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
24 * @dsc_disable: disable dsc
25 * @hw_dsc: Pointer to dsc context
30 * @dsc_config: configures dsc encoder
31 * @hw_dsc: Pointer to dsc context
32 * @dsc: panel dsc parameters
33 * @mode: dsc topology mode to be set
37 struct drm_dsc_config *dsc,
43 * @hw_dsc: Pointer to dsc context
44 * @dsc: panel dsc parameters
[all …]
|
| H A D | dpu_encoder.c | 141 * @hw_dsc: Handle to the DSC blocks used for the display.
142 * @dsc_mask: Bitmask of used DSC blocks.
172 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
216 /* DSC configuration */
217 struct drm_dsc_config *dsc; member
295 * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled
303 return dpu_enc->dsc ? true : false; in dpu_encoder_is_dsc_enabled()
619 * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology.
639 * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
640 * This helper function is used by physical encoder to get DSC config
[all …]
|
| H A D | dpu_rm.c | 169 const struct dpu_dsc_cfg *dsc = &cat->dsc[i]; in dpu_rm_init() local
172 hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio); in dpu_rm_init()
174 hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver); in dpu_rm_init()
178 DPU_ERROR("failed dsc object creation: err %d\n", rc); in dpu_rm_init()
181 rm->dsc_blks[dsc->id - DSC_0] = &hw->base; in dpu_rm_init()
512 * DSC with even index must be used with the PINGPONG with even index in _dpu_rm_pingpong_dsc_check()
513 * DSC with odd index must be used with the PINGPONG with odd index in _dpu_rm_pingpong_dsc_check()
553 DPU_ERROR("DSC allocation failed num_dsc=%d required=%d\n", in _dpu_rm_dsc_alloc()
570 /* only start from even dsc index */ in _dpu_rm_dsc_alloc_pair()
577 /* consective dsc index to be paired */ in _dpu_rm_dsc_alloc_pair()
[all …]
|
| H A D | dpu_hw_pingpong.h | 81 * @enable_dsc: Enable DSC
86 * @disable_dsc: Disable DSC
91 * @setup_dsc: Setup DSC
|
| H A D | dpu_hw_catalog.h | 142 * DSC sub-blocks/features
200 * struct dpu_dsc_blk - DSC Encoder sub-blk information
327 * struct dpu_dsc_sub_blks - DSC sub-blks
328 * @enc: DSC encoder sub-block
329 * @ctl: DSC controller sub-block
472 * struct dpu_dsc_cfg - information of DSC blocks
723 const struct dpu_dsc_cfg *dsc; member
|
| H A D | dpu_hw_ctl.h | 46 * @dsc: DSC BIT masks used
59 unsigned int dsc; member
314 * @pending_dsc_flush_mask: pending DSC flush
|
| /linux/drivers/gpu/drm/panel/ |
| H A D | panel-lg-sw43408.c | 33 struct drm_dsc_config dsc; member
106 drm_dsc_pps_payload_pack(&pps, sw43408->link->dsc); in sw43408_program()
275 /* The panel works only in the DSC mode. Set DSC params. */ in sw43408_probe()
276 ctx->dsc.dsc_version_major = 0x1; in sw43408_probe()
277 ctx->dsc.dsc_version_minor = 0x1; in sw43408_probe()
280 ctx->dsc.slice_height = 16; in sw43408_probe()
281 ctx->dsc.slice_width = 540; in sw43408_probe()
282 ctx->dsc.slice_count = 2; in sw43408_probe()
283 ctx->dsc.bits_per_component = 8; in sw43408_probe()
284 ctx->dsc.bits_per_pixel = 8 << 4; in sw43408_probe()
[all …]
|
| H A D | panel-novatek-nt37801.c | 23 struct drm_dsc_config dsc; member
146 drm_dsc_pps_payload_pack(&pps, &ctx->dsc); in novatek_nt37801_prepare()
290 /* This panel only supports DSC; unconditionally enable it */ in novatek_nt37801_probe()
291 dsi->dsc = &ctx->dsc; in novatek_nt37801_probe()
292 ctx->dsc.dsc_version_major = 1; in novatek_nt37801_probe()
293 ctx->dsc.dsc_version_minor = 1; in novatek_nt37801_probe()
294 ctx->dsc.slice_height = 40; in novatek_nt37801_probe()
295 ctx->dsc.slice_width = 720; in novatek_nt37801_probe()
296 ctx->dsc.slice_count = 1440 / ctx->dsc.slice_width; in novatek_nt37801_probe()
297 ctx->dsc.bits_per_component = 8; in novatek_nt37801_probe()
[all …]
|
| /linux/include/drm/display/ |
| H A D | drm_dsc.h | 13 /* VESA Display Stream Compression DSC 1.2 constants */
21 /* DSC Rate Control Constants */
27 /* DSC PPS constants and macros */
45 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
47 * This defines different rate control parameters used by the DSC engine
67 * struct drm_dsc_config - Parameters required to configure DSC
89 * @slice_count: Number fo slices per line used by the DSC encoder
239 * @dsc_version_minor: DSC minor version
243 * @dsc_version_major: DSC major version
276 * The VESA DSC standard defines picture parameter set (PPS) which display
[all …]
|
| H A D | drm_dsc_helper.h | 15 DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
30 u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc);
31 u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc);
|
| H A D | drm_dp_helper.h | 207 /* DP/eDP DSC support */
244 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format
245 * @dsc_dpcd : DSC-capability DPCDs of the sink
248 * Returns true if the sink supports DSC with the given output_format, false otherwise.
835 * The device supports MST DSC despite not supporting Virtual DPCD.
836 * The DSC caps can be read from the physical aux instead.
850 * requires enabling DSC.
856 * The device doesn't support DSC decompression at the maximum DSC
857 * pixel throughput and compressed bpp it indicates via its DPCD DSC
859 * specific DSC pixel throughput.
|
| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| H A D | dcn401_dsc.h | 8 #include "dsc.h"
9 #include "dsc/dscc_types.h"
13 #define TO_DCN401_DSC(dsc)\ argument
14 container_of(dsc, struct dcn401_dsc, base)
328 void dsc401_construct(struct dcn401_dsc *dsc,
337 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
338 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg…
339 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
341 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);
342 void dsc401_disable(struct display_stream_compressor *dsc);
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | Makefile | 11 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn20/,$(DSC_DCN20))
22 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn35/,$(DSC_DCN35))
30 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn401/,$(DSC_DCN401))
34 DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o macro
36 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
|
| H A D | rc_calc.c | 30 * @rc: DC internal DSC parameters
31 * @pps: DRM struct with all required DSC values
33 * This function expects a drm_dsc_config data struct with all the required DSC
35 * computes some of the DSC values.
|
| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.c | 273 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 in validate_dsc_caps_on_connector()
280 * because it only check the dsc/fec caps of the "port variable" and not the dock in validate_dsc_caps_on_connector()
282 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display in validate_dsc_caps_on_connector()
933 params[i].timing->flags.DSC = 1; in set_dsc_configs_from_fairness_vars()
946 params[i].timing->flags.DSC = 0; in set_dsc_configs_from_fairness_vars()
959 DRM_DEBUG_DRIVER("MST_DSC dsc=%d bits_per_pixel=%d pbn=%d\n", in set_dsc_configs_from_fairness_vars()
960 params[i].timing->flags.DSC, in set_dsc_configs_from_fairness_vars()
1154 DRM_DEBUG_DRIVER("MST_DSC index #%d, greedily disable dsc\n", next_index); in try_disable_dsc()
1182 DRM_DEBUG_DRIVER("MST_DSC DSC params: stream #%d --- dsc_enabled = %d, bpp_x16 = %d, pbn = %d\n", in log_dsc_params()
1233 stream->timing.flags.DSC = 0; in compute_mst_dsc_configs_for_link()
[all …]
|
| H A D | amdgpu_dm_helpers.c | 801 "MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
804 /* When DSC is enabled on previous boot and reboot with the hub, in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
814 DRM_INFO("MST_DSC Send DSC enable to synaptics\n"); in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
818 * external monitor occur garbage while disable DSC, in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
819 * Disable DSC only when entire link status turn to false, in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
823 DRM_INFO("MST_DSC Send DSC disable to synaptics\n"); in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
865 "MST_DSC Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
872 "MST_DSC Sent DSC decoding enable to %s port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
880 "MST_DSC Sent DSC decoding disable to %s port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
890 "MST_DSC Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dsc.h | 28 /* DP Extended DSC Capabilities */
71 const struct display_stream_compressor *dsc,
81 const struct display_stream_compressor *dsc,
97 void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,
99 void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,
102 /* TODO - Hardware/specs limitation should be owned by dc dsc and returned to DM,
|
| H A D | dc_hw_types.h | 811 uint32_t DSC : 1; /* Use DSC with this timing */ member
861 uint32_t num_slices_h; /* Number of DSC slices - horizontal */
862 uint32_t num_slices_v; /* Number of DSC slices - vertical */
863 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
864 bool block_pred_enable; /* DSC block prediction enable */
865 uint32_t linebuf_depth; /* DSC line buffer depth */
866 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */
867 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
868 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
869 bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 54 #include "dsc.h"
750 static void dsc_optc_config_log(struct display_stream_compressor *dsc, in dsc_optc_config_log() argument
757 DC_LOGGER_INIT(dsc->ctx->logger); in dsc_optc_config_log()
759 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC in dsc_optc_config_log()
799 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
807 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream() local
817 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger in link_set_dsc_on_stream()
824 DC_LOGGER_INIT(dsc->ctx->logger); in link_set_dsc_on_stream()
834 /* Enable DSC hw block */ in link_set_dsc_on_stream()
847 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in link_set_dsc_on_stream()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 36 #include "dsc.h"
2260 struct display_stream_compressor *dsc = params->dsc_set_config_params.dsc; in hwss_dsc_set_config() local
2264 if (dsc && dsc->funcs->dsc_set_config) in hwss_dsc_set_config()
2265 dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg); in hwss_dsc_set_config()
2270 struct display_stream_compressor *dsc = params->dsc_enable_params.dsc; in hwss_dsc_enable() local
2273 if (dsc && dsc->funcs->dsc_enable) in hwss_dsc_enable()
2274 dsc->funcs->dsc_enable(dsc, opp_inst); in hwss_dsc_enable()
2301 struct display_stream_compressor *dsc = params->dsc_disconnect_params.dsc; in hwss_dsc_disconnect() local
2303 if (dsc && dsc->funcs->dsc_disconnect) in hwss_dsc_disconnect()
2304 dsc->funcs->dsc_disconnect(dsc); in hwss_dsc_disconnect()
[all …]
|
| /linux/drivers/gpu/drm/tests/ |
| H A D | drm_dp_mst_helper_test.c | 18 const bool dsc; member
26 .dsc = false,
32 .dsc = false,
38 .dsc = false,
44 .dsc = true,
50 .dsc = true,
65 sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled"); in dp_mst_calc_pbn_mode_desc()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 27 #include "dsc.h"
1541 // old_otg_master to NULL to skip the DSC configuration. in update_dsc_for_odm_change()
1546 if (otg_master->stream_res.dsc) in update_dsc_for_odm_change()
1548 otg_master->stream->timing.flags.DSC); in update_dsc_for_odm_change()
1549 if (old_otg_master && old_otg_master->stream_res.dsc) { in update_dsc_for_odm_change()
1553 if (old_pipe->stream_res.dsc && !new_pipe->stream_res.dsc) in update_dsc_for_odm_change()
1554 old_pipe->stream_res.dsc->funcs->dsc_disconnect( in update_dsc_for_odm_change()
1555 old_pipe->stream_res.dsc); in update_dsc_for_odm_change()
1625 /* Process new DSC configuration if DSC is enabled */ in dcn401_add_dsc_sequence_for_odm_change()
1626 if (otg_master->stream_res.dsc && otg_master->stream->timing.flags.DSC) { in dcn401_add_dsc_sequence_for_odm_change()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
| H A D | dcn20_optc.c | 127 /* Set DSC-related configuration.
128 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
149 /* Get DSC-related configuration.
150 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
|
| /linux/drivers/scsi/qla2xxx/ |
| H A D | qla_mid.c | 1136 int qla_get_buf(struct scsi_qla_host *vha, struct qla_qpair *qp, struct qla_buf_dsc *dsc) in qla_get_buf() argument
1143 dsc->tag = TAG_FREED; in qla_get_buf()
1170 dsc->buf = qp->buf_pool.buf_array[tag] = buf; in qla_get_buf()
1171 dsc->buf_dma = qp->buf_pool.dma_array[tag] = buf_dma; in qla_get_buf()
1174 dsc->buf = qp->buf_pool.buf_array[tag]; in qla_get_buf()
1175 dsc->buf_dma = qp->buf_pool.dma_array[tag]; in qla_get_buf()
1176 memset(dsc->buf, 0, FCP_CMND_DMA_POOL_SIZE); in qla_get_buf()
1183 dsc->tag = tag; in qla_get_buf()
1242 void qla_put_buf(struct qla_qpair *qp, struct qla_buf_dsc *dsc) in qla_put_buf() argument
1244 if (dsc->tag == TAG_FREED) in qla_put_buf()
[all …]
|
| /linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | anx7625.h | 230 #define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */
231 #define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */
361 /* For DSC only */
363 /* For DSC only; note: bit[7:6] are reserved */
|