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/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c9 #include "dsc/dscc_types.h"
10 #include "dsc/rc_calc.h"
12 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_valu…
16 //static bool dsc401_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config …
42 dsc->ctx->logger
47 void dsc401_construct(struct dcn401_dsc *dsc, in dsc401_construct() argument
54 dsc->base.ctx = ctx; in dsc401_construct()
55 dsc->base.inst = inst; in dsc401_construct()
56 dsc->base.funcs = &dcn401_dsc_funcs; in dsc401_construct()
58 dsc->dsc_regs = dsc_regs; in dsc401_construct()
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H A Ddcn401_dsc.h8 #include "dsc.h"
9 #include "dsc/dscc_types.h"
13 #define TO_DCN401_DSC(dsc)\ argument
14 container_of(dsc, struct dcn401_dsc, base)
328 void dsc401_construct(struct dcn401_dsc *dsc,
337 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
338 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg…
339 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
341 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);
342 void dsc401_disable(struct display_stream_compressor *dsc);
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/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn35/
H A Ddcn35_dsc.c30 static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe);
57 dsc->ctx->logger
59 void dsc35_construct(struct dcn20_dsc *dsc, in dsc35_construct() argument
66 dsc->base.ctx = ctx; in dsc35_construct()
67 dsc->base.inst = inst; in dsc35_construct()
68 dsc->base.funcs = &dcn35_dsc_funcs; in dsc35_construct()
70 dsc->dsc_regs = dsc_regs; in dsc35_construct()
71 dsc->dsc_shift = (const struct dcn20_dsc_shift *)(dsc_shift); in dsc35_construct()
72 dsc->dsc_mask = (const struct dcn20_dsc_mask *)(dsc_mask); in dsc35_construct()
74 dsc->max_image_width = 5184; in dsc35_construct()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddsc.h36 /* Input parameters for configuring DSC from the outside of DSC */
47 /* Output parameters for configuring DSC-related part of OPTC */
69 /* DSC encoder capabilities
70 * They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps.
76 uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */
101 void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
102 …bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cf…
103 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
105 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
107 void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
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H A DMakefile11 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn20/,$(DSC_DCN20))
22 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn35/,$(DSC_DCN35))
30 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn401/,$(DSC_DCN401))
34 DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o macro
36 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
H A Drc_calc.c30 * @rc: DC internal DSC parameters
31 * @pps: DRM struct with all required DSC values
33 * This function expects a drm_dsc_config data struct with all the required DSC
35 * computes some of the DSC values.
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.c54 #include "dsc.h"
74 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() local
79 ASSERT(dsc); in update_dsc_on_stream()
89 if (!dsc) { in update_dsc_on_stream()
90 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
94 if (dsc->funcs->dsc_read_state) { in update_dsc_on_stream()
95 dsc->funcs->dsc_read_state(dsc, &dsc_state); in update_dsc_on_stream()
97 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
102 /* Enable DSC hw block */ in update_dsc_on_stream()
112 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
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/linux/drivers/gpu/drm/panel/
H A Dpanel-lg-sw43408.c33 struct drm_dsc_config dsc; member
106 drm_dsc_pps_payload_pack(&pps, sw43408->link->dsc); in sw43408_program()
275 /* The panel works only in the DSC mode. Set DSC params. */ in sw43408_probe()
276 ctx->dsc.dsc_version_major = 0x1; in sw43408_probe()
277 ctx->dsc.dsc_version_minor = 0x1; in sw43408_probe()
280 ctx->dsc.slice_height = 16; in sw43408_probe()
281 ctx->dsc.slice_width = 540; in sw43408_probe()
282 ctx->dsc.slice_count = 2; in sw43408_probe()
283 ctx->dsc.bits_per_component = 8; in sw43408_probe()
284 ctx->dsc.bits_per_pixel = 8 << 4; in sw43408_probe()
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H A Dpanel-novatek-nt37801.c23 struct drm_dsc_config dsc; member
146 drm_dsc_pps_payload_pack(&pps, &ctx->dsc); in novatek_nt37801_prepare()
290 /* This panel only supports DSC; unconditionally enable it */ in novatek_nt37801_probe()
291 dsi->dsc = &ctx->dsc; in novatek_nt37801_probe()
292 ctx->dsc.dsc_version_major = 1; in novatek_nt37801_probe()
293 ctx->dsc.dsc_version_minor = 1; in novatek_nt37801_probe()
294 ctx->dsc.slice_height = 40; in novatek_nt37801_probe()
295 ctx->dsc.slice_width = 720; in novatek_nt37801_probe()
296 ctx->dsc.slice_count = 1440 / ctx->dsc.slice_width; in novatek_nt37801_probe()
297 ctx->dsc.bits_per_component = 8; in novatek_nt37801_probe()
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/linux/include/drm/display/
H A Ddrm_dsc.h13 /* VESA Display Stream Compression DSC 1.2 constants */
21 /* DSC Rate Control Constants */
27 /* DSC PPS constants and macros */
45 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
47 * This defines different rate control parameters used by the DSC engine
67 * struct drm_dsc_config - Parameters required to configure DSC
89 * @slice_count: Number fo slices per line used by the DSC encoder
239 * @dsc_version_minor: DSC minor version
243 * @dsc_version_major: DSC major version
276 * The VESA DSC standard defines picture parameter set (PPS) which display
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H A Ddrm_dsc_helper.h15 DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
30 u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc);
31 u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c54 #include "dsc.h"
329 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() local
336 ASSERT(dsc); in update_dsc_on_stream()
346 if (!dsc) { in update_dsc_on_stream()
347 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
351 if (dsc->funcs->dsc_read_state) { in update_dsc_on_stream()
352 dsc->funcs->dsc_read_state(dsc, &dsc_state); in update_dsc_on_stream()
354 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
358 /* Enable DSC hw block */ in update_dsc_on_stream()
368 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c273 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 in validate_dsc_caps_on_connector()
280 * because it only check the dsc/fec caps of the "port variable" and not the dock in validate_dsc_caps_on_connector()
282 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display in validate_dsc_caps_on_connector()
933 params[i].timing->flags.DSC = 1; in set_dsc_configs_from_fairness_vars()
946 params[i].timing->flags.DSC = 0; in set_dsc_configs_from_fairness_vars()
959 DRM_DEBUG_DRIVER("MST_DSC dsc=%d bits_per_pixel=%d pbn=%d\n", in set_dsc_configs_from_fairness_vars()
960 params[i].timing->flags.DSC, in set_dsc_configs_from_fairness_vars()
1154 DRM_DEBUG_DRIVER("MST_DSC index #%d, greedily disable dsc\n", next_index); in try_disable_dsc()
1182 DRM_DEBUG_DRIVER("MST_DSC DSC params: stream #%d --- dsc_enabled = %d, bpp_x16 = %d, pbn = %d\n", in log_dsc_params()
1233 stream->timing.flags.DSC = 0; in compute_mst_dsc_configs_for_link()
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dsc.h28 /* DP Extended DSC Capabilities */
71 const struct display_stream_compressor *dsc,
81 const struct display_stream_compressor *dsc,
97 void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,
99 void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,
102 /* TODO - Hardware/specs limitation should be owned by dc dsc and returned to DM,
H A Ddc_hw_types.h811 uint32_t DSC : 1; /* Use DSC with this timing */ member
861 uint32_t num_slices_h; /* Number of DSC slices - horizontal */
862 uint32_t num_slices_v; /* Number of DSC slices - vertical */
863 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
864 bool block_pred_enable; /* DSC block prediction enable */
865 uint32_t linebuf_depth; /* DSC line buffer depth */
866 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */
867 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
868 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
869 bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder.c140 * @hw_dsc: Handle to the DSC blocks used for the display.
141 * @dsc_mask: Bitmask of used DSC blocks.
171 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
215 /* DSC configuration */
216 struct drm_dsc_config *dsc; member
294 * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled
302 return dpu_enc->dsc ? true : false; in dpu_encoder_is_dsc_enabled()
618 * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology.
638 * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
639 * This helper function is used by physical encoder to get DSC config
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/linux/drivers/gpu/drm/tests/
H A Ddrm_dp_mst_helper_test.c18 const bool dsc; member
26 .dsc = false,
32 .dsc = false,
38 .dsc = false,
44 .dsc = true,
50 .dsc = true,
65 sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled"); in dp_mst_calc_pbn_mode_desc()
/linux/include/linux/irqchip/
H A Dirq-partition-percpu.h28 struct irq_domain *partition_get_domain(struct partition_desc *dsc);
47 struct irq_domain *partition_get_domain(struct partition_desc *dsc) in partition_get_domain() argument
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.c127 /* Set DSC-related configuration.
128 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
149 /* Get DSC-related configuration.
150 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
/linux/drivers/scsi/qla2xxx/
H A Dqla_mid.c1138 int qla_get_buf(struct scsi_qla_host *vha, struct qla_qpair *qp, struct qla_buf_dsc *dsc) in qla_get_buf() argument
1145 dsc->tag = TAG_FREED; in qla_get_buf()
1172 dsc->buf = qp->buf_pool.buf_array[tag] = buf; in qla_get_buf()
1173 dsc->buf_dma = qp->buf_pool.dma_array[tag] = buf_dma; in qla_get_buf()
1176 dsc->buf = qp->buf_pool.buf_array[tag]; in qla_get_buf()
1177 dsc->buf_dma = qp->buf_pool.dma_array[tag]; in qla_get_buf()
1178 memset(dsc->buf, 0, FCP_CMND_DMA_POOL_SIZE); in qla_get_buf()
1185 dsc->tag = tag; in qla_get_buf()
1244 void qla_put_buf(struct qla_qpair *qp, struct qla_buf_dsc *dsc) in qla_put_buf() argument
1246 if (dsc->tag == TAG_FREED) in qla_put_buf()
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.h230 #define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */
231 #define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */
361 /* For DSC only */
363 /* For DSC only; note: bit[7:6] are reserved */
/linux/drivers/irqchip/
H A Dirq-partition-percpu.c235 struct irq_domain *partition_get_domain(struct partition_desc *dsc) in partition_get_domain() argument
237 if (dsc) in partition_get_domain()
238 return dsc->domain; in partition_get_domain()
/linux/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
H A Dktls_stats.c50 #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ argument
51 atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))
/linux/Documentation/networking/device_drivers/ethernet/amd/
H A Dpds_vfio_pci.rst5 PCI VFIO driver for the AMD/Pensando(R) DSC adapter family
15 capable Virtual Function (VF) devices in the DSC hardware.
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c358 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) in dccg31_disable_dscclk()
402 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) in dccg31_enable_dscclk()
555 * non-DSC 4:2:0 mode pixel rate/2 4 in dccg31_set_dtbclk_dto()
556 * DSC native 4:2:0 pixel rate/2 4 in dccg31_set_dtbclk_dto()
557 * DSC native 4:2:2 pixel rate/2 4 in dccg31_set_dtbclk_dto()
565 (params->timing->flags.DSC && params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 in dccg31_set_dtbclk_dto()

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