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/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", 47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) i [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", 47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) i [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", 47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) i [all...]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 16 "PublicDescription": "Number of DSB to MITE switches.", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 25 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 30 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 34 "PublicDescription": "DSB Fill encountered > 3 DSB lines.", 66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 71 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 81 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", [all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 16 "PublicDescription": "Number of DSB to MITE switches.", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 25 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 30 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 34 "PublicDescription": "DSB Fill encountered > 3 DSB lines.", 66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 71 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 81 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 39 "BriefDescription": "Retired Instructions who experienced DSB miss.", 46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 51 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is… 303 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ… [all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 39 "BriefDescription": "Retired Instructions who experienced DSB miss.", 46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 51 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is… 303 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ… [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 39 "BriefDescription": "Retired Instructions who experienced DSB miss.", 46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 51 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is… 303 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ… [all …]
/linux/arch/arm64/kvm/hyp/nvhe/
H A D	tlb.c	35 * CPUs, for which a dsb(DOMAIN-st) is what we need, DOMAIN in enter_vmid_context() 41 * registers out of context, for which dsb(nsh) is enough in enter_vmid_context() 43 * The composition of these two barriers is a dsb(DOMAIN), and in enter_vmid_context() 49 dsb(nsh); in enter_vmid_context() 51 dsb(ish); in enter_vmid_context() 170 dsb(ish); in __kvm_tlb_flush_vmid_ipa() 172 dsb(ish); in __kvm_tlb_flush_vmid_ipa() 200 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh() 202 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh() 227 dsb(ish); in __kvm_tlb_flush_vmid_range() [all …]
/linux/arch/arm64/kvm/hyp/vhe/
H A D	tlb.c	`97 dsb(ishst); in __kvm_tlb_flush_vmid_ipa() 116 dsb(ish); in __kvm_tlb_flush_vmid_ipa() 118 dsb(ish); in __kvm_tlb_flush_vmid_ipa() 129 dsb(nshst); in __kvm_tlb_flush_vmid_ipa_nsh() 148 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh() 150 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh() 169 dsb(ishst); in __kvm_tlb_flush_vmid_range() 177 dsb(ish); in __kvm_tlb_flush_vmid_range() 179 dsb(ish); in __kvm_tlb_flush_vmid_range() 189 dsb(ishst); in __kvm_tlb_flush_vmid() [all …]`
/linux/fs/erofs/
H A D	super.c	42 struct erofs_super_block dsb = sbdata + EROFS_SUPER_OFFSET; in erofs_superblock_csum_verify() local 48 sizeof(dsb->checksum); in erofs_superblock_csum_verify() 51 crc = crc32c(0x5045B54A, (&dsb->checksum) + 1, len); in erofs_superblock_csum_verify() 52 if (crc == le32_to_cpu(dsb->checksum)) in erofs_superblock_csum_verify() 55 crc, le32_to_cpu(dsb->checksum)); in erofs_superblock_csum_verify() 126 struct erofs_super_block dsb) in z_erofs_parse_cfgs() argument 128 if (!dsb->u1.available_compr_algs) in z_erofs_parse_cfgs() 197 struct erofs_super_block dsb) in erofs_scan_devices() argument 210 ondisk_extradevs = le16_to_cpu(dsb->extra_devices); in erofs_scan_devices() 230 pos = le16_to_cpu(dsb->devt_slotoff) EROFS_DEVT_SLOT_SIZE; in erofs_scan_devices() [all …]
/linux/arch/arm64/include/asm/
H A D	tlbflush.h	`35 "dsb ish\n tlbi " #op, \ 43 "dsb ish\n tlbi " #op ", %0", \ 193 * DSB ISHST // Ensure prior page-table updates have completed 195 * DSB ISH // Ensure the TLB invalidation has completed 259 dsb(nshst); in local_flush_tlb_all() 261 dsb(nsh); in local_flush_tlb_all() 267 dsb(ishst); in flush_tlb_all() 269 dsb(ish); in flush_tlb_all() 277 dsb(ishst); in flush_tlb_mm() 281 dsb(ish); in flush_tlb_mm() [all …]`
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod… 28 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 36 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 44 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", 69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 78 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 105 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 114 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", [all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod… 28 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 36 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 44 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", 69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 78 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 105 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 114 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", [all …]
/linux/arch/arm/include/asm/
H A D	barrier.h	`20 #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") macro 31 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro 38 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro 43 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro 58 #define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0) 60 #define __arm_heavy_mb(x...) dsb(x) 65 #define rmb() dsb()`
/linux/arch/arm/mach-omap2/
H A D	sleep43xx.S	`99 dsb 114 dsb 116 dsb 138 dsb 140 dsb 262 dsb 388 dsb 390 dsb 394 dsb 396 dsb [all …]`
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", 41 "BriefDescription": "Retired Instructions who experienced DSB miss.", 47 "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB mis [all...]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", 41 "BriefDescription": "Retired Instructions who experienced DSB miss.", 47 "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB mis [all...]
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", 41 "BriefDescription": "Retired Instructions who experienced DSB miss.", 47 "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB mis [all...]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", 41 "BriefDescription": "Retired Instructions who experienced DSB miss.", 47 "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB mis [all...]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 53 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 58 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 68 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 93 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 102 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 106 …"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = … 158 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered … 167 …eries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Se… [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 53 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 58 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 68 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 93 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 102 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 106 …"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = … 158 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered … 167 …eries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Se… [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	frontend.json	29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 33 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b… 49 "BriefDescription": "Retired Instructions who experienced DSB miss.", 55 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 63 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 69 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 329 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 334 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", 339 "BriefDescription": "Cycles DSB is delivering optimal number of Uops", 344 …umber of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buff… [all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	frontend.json	29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 33 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b… 38 "BriefDescription": "Retired Instructions who experienced DSB miss.", 44 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 49 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 55 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 275 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 280 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", 285 "BriefDescription": "Cycles DSB is delivering optimal number of Uops", 290 …umber of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buff… [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	frontend.json	29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 33 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b… 38 "BriefDescription": "Retired Instructions who experienced DSB miss.", 44 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 49 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 55 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 275 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 280 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", 285 "BriefDescription": "Cycles DSB is delivering optimal number of Uops", 290 …umber of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buff… [all …]

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