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/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", 47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) i [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", 47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) i [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", 47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) i [all...]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 16 "PublicDescription": "Number of DSB to MITE switches.", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 25 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 30 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 34 "PublicDescription": "DSB Fill encountered > 3 DSB lines.", 66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 71 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 81 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", [all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 16 "PublicDescription": "Number of DSB to MITE switches.", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 25 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 30 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 34 "PublicDescription": "DSB Fill encountered > 3 DSB lines.", 66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 71 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 81 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", [all …]
/linux/drivers/hwtracing/coresight/
H A D	coresight-tpdm.c	51 drvdata->dsb->edge_ctrl[tpdm_attr->idx]); in tpdm_simple_dataset_show() 56 drvdata->dsb->edge_ctrl_mask[tpdm_attr->idx]); in tpdm_simple_dataset_show() 61 drvdata->dsb->trig_patt[tpdm_attr->idx]); in tpdm_simple_dataset_show() 66 drvdata->dsb->trig_patt_mask[tpdm_attr->idx]); in tpdm_simple_dataset_show() 71 drvdata->dsb->patt_val[tpdm_attr->idx]); in tpdm_simple_dataset_show() 76 drvdata->dsb->patt_mask[tpdm_attr->idx]); in tpdm_simple_dataset_show() 81 drvdata->dsb->msr[tpdm_attr->idx]); in tpdm_simple_dataset_show() 131 drvdata->dsb->trig_patt[tpdm_attr->idx] = val; in tpdm_simple_dataset_store() 137 drvdata->dsb->trig_patt_mask[tpdm_attr->idx] = val; in tpdm_simple_dataset_store() 143 drvdata->dsb->patt_val[tpdm_attr->idx] = val; in tpdm_simple_dataset_store() [all …]
H A D	coresight-tpdm.h	`45 /* MAX number of DSB MSR / 54 / DSB Subunit Registers / 65 / Enable bit for DSB subunit / 67 / Enable bit for DSB subunit perfmance mode / 69 / Enable bit for DSB subunit trigger type / 71 / Data bits for DSB high performace mode / 73 / Data bits for DSB test mode / 76 / Enable bit for DSB subunit pattern timestamp / 78 / Enable bit for DSB subunit trigger timestamp / 80 / Bit for DSB subunit pattern type */ [all …]`
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 39 "BriefDescription": "Retired Instructions who experienced DSB miss.", 46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 51 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is… 303 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ… [all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 39 "BriefDescription": "Retired Instructions who experienced DSB miss.", 46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 51 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is… 303 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ… [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 39 "BriefDescription": "Retired Instructions who experienced DSB miss.", 46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 51 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is… 303 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ… [all …]
/linux/Documentation/ABI/testing/
H A D	sysfs-bus-coresight-devices-tpdm	30 (RW) Set/Get the trigger type of the DSB for tpdm. 33 0 : Set the DSB trigger type to false 34 1 : Set the DSB trigger type to true 41 (RW) Set/Get the trigger timestamp of the DSB for tpdm. 44 0 : Set the DSB trigger type to false 45 1 : Set the DSB trigger type to true 52 (RW) Set/Get the programming mode of the DSB for tpdm. 66 (RW) Set/Get the index number of the edge detection for the DSB 103 Read a set of the edge control value of the DSB in TPDM. 110 Read a set of the edge control mask of the DSB in TPDM. [all …]
/linux/fs/erofs/
H A D	super.c	43 struct erofs_super_block dsb = sbdata + EROFS_SUPER_OFFSET; in erofs_superblock_csum_verify() local 49 sizeof(dsb->checksum); in erofs_superblock_csum_verify() 52 crc = crc32c(0x5045B54A, (&dsb->checksum) + 1, len); in erofs_superblock_csum_verify() 53 if (crc == le32_to_cpu(dsb->checksum)) in erofs_superblock_csum_verify() 56 crc, le32_to_cpu(dsb->checksum)); in erofs_superblock_csum_verify() 190 struct erofs_super_block dsb) in erofs_scan_devices() argument 203 ondisk_extradevs = le16_to_cpu(dsb->extra_devices); in erofs_scan_devices() 223 pos = le16_to_cpu(dsb->devt_slotoff) * EROFS_DEVT_SLOT_SIZE; in erofs_scan_devices() 260 struct erofs_super_block dsb; in erofs_read_superblock() local 270 dsb = (struct erofs_super_block )(data + EROFS_SUPER_OFFSET); in erofs_read_superblock() [all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod… 28 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 36 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 44 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", 69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 78 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 105 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 114 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", [all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod… 28 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 36 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 44 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", 69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 78 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 105 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 114 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", [all …]
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", 41 "BriefDescription": "Retired Instructions who experienced DSB miss.", 47 "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB mis [all...]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", 41 "BriefDescription": "Retired Instructions who experienced DSB miss.", 47 "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB mis [all...]
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", 41 "BriefDescription": "Retired Instructions who experienced DSB miss.", 47 "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB mis [all...]
/linux/arch/arm/mach-omap2/
H A D	sleep43xx.S	`99 dsb 114 dsb 116 dsb 138 dsb 140 dsb 262 dsb 388 dsb 390 dsb 394 dsb 396 dsb [all …]`
/linux/arch/arm/include/asm/
H A D	barrier.h	`20 #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") macro 31 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro 38 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro 43 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro 58 #define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0) 60 #define __arm_heavy_mb(x...) dsb(x) 65 #define rmb() dsb()`
/linux/arch/arm64/kvm/hyp/nvhe/
H A D	tlb.c	35 * CPUs, for which a dsb(DOMAIN-st) is what we need, DOMAIN in enter_vmid_context() 41 * registers out of context, for which dsb(nsh) is enough in enter_vmid_context() 43 * The composition of these two barriers is a dsb(DOMAIN), and in enter_vmid_context() 49 dsb(nsh); in enter_vmid_context() 51 dsb(ish); in enter_vmid_context() 169 dsb(ish); in __kvm_tlb_flush_vmid_ipa() 198 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh() 200 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh() 225 dsb(ish); in __kvm_tlb_flush_vmid_range() 256 dsb(nsh); in __kvm_flush_cpu_context() [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", 32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 36 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", 41 "BriefDescription": "Retired Instructions who experienced DSB miss.", 47 "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 58 "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB mis [all...]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 53 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 58 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 68 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 93 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 102 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 106 …"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = … 158 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered … 167 …eries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Se… [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 53 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 58 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 68 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 93 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 102 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 106 …"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = … 158 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered … 167 …eries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Se… [all …]
/linux/arch/arm64/include/asm/
H A D	tlbflush.h	`104 dsb(ish); in sme_dvmsync_add_pending() 274 dsb(ish); \ 283 dsb(ish); in __tlbi_sync_s1ish() 290 dsb(ish); in __tlbi_sync_s1ish_batch() 297 dsb(ish); in __tlbi_sync_s1ish_kernel() 307 dsb(ish); in __tlbi_sync_s1ish_hyp() 320 * DSB ISHST // Ensure prior page-table updates have completed 322 * DSB ISH // Ensure the TLB invalidation has completed 376 * TLBF_NOSYNC (don't issue trailing dsb) and TLBF_NOBROADCAST 385 * TLBF_NOSYNC (don't issue trailing dsb) and TLBF_NOBROADCAST [all …]`
/linux/arch/arm64/kvm/hyp/vhe/
H A D	tlb.c	`97 dsb(ishst); in __kvm_tlb_flush_vmid_ipa() 115 dsb(ish); in __kvm_tlb_flush_vmid_ipa() 128 dsb(nshst); in __kvm_tlb_flush_vmid_ipa_nsh() 146 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh() 148 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh() 167 dsb(ishst); in __kvm_tlb_flush_vmid_range() 175 dsb(ish); in __kvm_tlb_flush_vmid_range() 187 dsb(ishst); in __kvm_tlb_flush_vmid() 208 dsb(nsh); in __kvm_flush_cpu_context() 216 dsb(ishst); in __kvm_flush_vm_context() [all …]`

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