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/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c142 * Context: Called under pf->dplls.lock
194 * Context: Acquires pf->dplls.lock
214 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_set()
216 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_set()
232 * Context: Calls a function which acquires pf->dplls.lock
257 * Context: Calls a function which acquires pf->dplls.lock
283 * Context: Acquires pf->dplls.lock
298 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_get()
300 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_get()
316 * Context: Calls a function which acquires pf->dplls.lock
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H A Dice_dpll.h109 * @clock_id: clock_id of dplls
H A Dice.h524 ICE_FLAG_DPLL, /* SyncE/PTP dplls initialized */
667 struct ice_dplls dplls;
665 struct ice_dplls dplls; global() member
/linux/drivers/dpll/zl3073x/
H A Dcore.c744 list_for_each_entry(zldpll, &zldev->dplls, list) in zl3073x_dev_periodic_work()
783 * and enable DPLL-to-its-ref phase measurement for all DPLLs.
813 list_for_each_entry(zldpll, &zldev->dplls, list) in zl3073x_dev_phase_meas_setup()
824 * The function starts normal operation, which means registering all DPLLs and
872 /* Register all DPLLs */ in zl3073x_dev_start()
873 list_for_each_entry(zldpll, &zldev->dplls, list) { in zl3073x_dev_start()
902 * DPLLs and their pins and stop monitoring.
913 /* Unregister all DPLLs */ in zl3073x_dev_stop()
914 list_for_each_entry(zldpll, &zldev->dplls, list) { in zl3073x_dev_stop()
925 /* Stop monitoring and unregister DPLLs */ in zl3073x_dev_dpll_fini()
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H A Ddpll.c1212 list_for_each_entry(item, &zldpll->dev->dplls, list) { in zl3073x_dpll_phase_offset_avg_factor_set()
/linux/arch/arm/mach-omap2/
H A Dclock.c85 /* Fint setup for DPLLs */ in ti_clk_init_features()
96 /* Bypass value setup for DPLLs */ in ti_clk_init_features()
H A Dcm2xxx.c24 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
/linux/include/linux/clk/
H A Dti.h75 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
79 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
161 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
/linux/Documentation/devicetree/bindings/dpll/
H A Ddpll-device.yaml15 have one or more channels (DPLLs) and one or more physical input and
/linux/drivers/gpu/drm/i915/display/
H A Dintel_lvds_regs.h14 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
H A Dintel_display_types.h1126 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
/linux/drivers/dpll/
H A Ddpll_core.h45 * @dpll_refs: hold referencees to dplls pin was registered with
H A Ddpll_core.c724 * between newly registered pin and dplls connected with a parent pin.
/linux/drivers/clk/ti/
H A Dclkt_dpll.c228 * DPLLs can be locked or bypassed - basically, enabled or disabled.
231 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
H A Ddpll3xxx.c420 /* Configure dco and sd_div for dplls that have these fields */ in omap3_noncore_dpll_program()
506 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c226 /* The LVDS pin pair needs to be on before the DPLLs are enabled. in psb_intel_crtc_mode_set()
240 * set the DPLLs for dual-channel mode or not. in psb_intel_crtc_mode_set()
H A Dcdv_intel_display.c731 /* The LVDS pin pair needs to be on before the DPLLs are enabled. in cdv_intel_crtc_mode_set()
743 * set the DPLLs for dual-channel mode or not. in cdv_intel_crtc_mode_set()
H A Dpsb_intel_reg.h438 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
/linux/arch/arm/boot/dts/ti/omap/
H A Ddm814x-clocks.dtsi5 * See TRM "2.6.10 Connected outputso DPLLS" and
/linux/drivers/ata/
H A Dpata_hpt3x2n.c92 * different DPLLs