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/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c152 * Context: Called under pf->dplls.lock
204 * Context: Acquires pf->dplls.lock
224 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_set()
226 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_set()
242 * Context: Calls a function which acquires pf->dplls.lock
267 * Context: Calls a function which acquires pf->dplls.lock
293 * Context: Acquires pf->dplls.lock
308 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_get()
310 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_get()
326 * Context: Calls a function which acquires pf->dplls.lock
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H A Dice.h524 ICE_FLAG_DPLL, /* SyncE/PTP dplls initialized */
667 struct ice_dplls dplls; member
H A Dice_ptp.c1299 mutex_lock(&pf->dplls.lock); in ice_ptp_link_change()
1326 mutex_unlock(&pf->dplls.lock); in ice_ptp_link_change()
3098 * ice_ptp_init() before pf->dplls.lock exists and before any in ice_ptp_setup_pf()
/linux/drivers/dpll/zl3073x/
H A Dcore.c734 list_for_each_entry(zldpll, &zldev->dplls, list) in zl3073x_dev_periodic_work()
772 * and enable DPLL-to-its-ref phase measurement for all DPLLs.
802 list_for_each_entry(zldpll, &zldev->dplls, list) in zl3073x_dev_phase_meas_setup()
813 * The function starts normal operation, which means registering all DPLLs and
861 /* Register all DPLLs */ in zl3073x_dev_start()
862 list_for_each_entry(zldpll, &zldev->dplls, list) { in zl3073x_dev_start()
891 * DPLLs and their pins and stop monitoring.
902 /* Unregister all DPLLs */ in zl3073x_dev_stop()
903 list_for_each_entry(zldpll, &zldev->dplls, list) { in zl3073x_dev_stop()
914 /* Stop monitoring and unregister DPLLs */ in zl3073x_dev_dpll_fini()
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H A Dcore.h68 * @dplls: list of DPLLs
91 struct list_head dplls; member
H A Ddpll.c335 list_for_each_entry(zldpll, &zldev->dplls, list) { in zl3073x_dpll_input_pin_ref_sync_set()
1412 list_for_each_entry(item, &zldpll->dev->dplls, list) { in zl3073x_dpll_phase_offset_avg_factor_set()
1562 list_for_each_entry(item, &zldev->dplls, list) { in zl3073x_dpll_freq_monitor_set()
1878 * - tie_clear: PPS DPLLs re-align outputs on NCO exit in zl3073x_dpll_nco_pin_register()
/linux/arch/arm/mach-omap2/
H A Dclock.c85 /* Fint setup for DPLLs */ in ti_clk_init_features()
96 /* Bypass value setup for DPLLs */ in ti_clk_init_features()
H A Dcm2xxx.c24 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
/linux/include/linux/clk/
H A Dti.h75 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
79 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
161 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
/linux/Documentation/devicetree/bindings/dpll/
H A Ddpll-device.yaml15 have one or more channels (DPLLs) and one or more physical input and
/linux/drivers/gpu/drm/i915/display/
H A Dintel_lvds_regs.h14 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
H A Dintel_ddi.c4459 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", in intel_ddi_initial_fastset_check()
/linux/drivers/dpll/
H A Ddpll_core.h50 * @dpll_refs: hold referencees to dplls pin was registered with
H A Ddpll_core.c982 * between newly registered pin and dplls connected with a parent pin.
1163 * also registered with dplls from other drivers.
/linux/drivers/clk/ti/
H A Dclkt_dpll.c228 * DPLLs can be locked or bypassed - basically, enabled or disabled.
231 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
H A Ddpll3xxx.c420 /* Configure dco and sd_div for dplls that have these fields */ in omap3_noncore_dpll_program()
506 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
H A Dclk.c449 * typically happens only for DPLLs which need to have both of their
/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c226 /* The LVDS pin pair needs to be on before the DPLLs are enabled. in psb_intel_crtc_mode_set()
240 * set the DPLLs for dual-channel mode or not. in psb_intel_crtc_mode_set()
H A Dcdv_intel_display.c731 /* The LVDS pin pair needs to be on before the DPLLs are enabled. in cdv_intel_crtc_mode_set()
743 * set the DPLLs for dual-channel mode or not. in cdv_intel_crtc_mode_set()
H A Dpsb_intel_reg.h438 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
/linux/arch/arm/boot/dts/ti/omap/
H A Ddm814x-clocks.dtsi5 * See TRM "2.6.10 Connected outputso DPLLS" and
/linux/Documentation/driver-api/
H A Ddpll.rst36 ``DPLL_CMD_DEVICE_GET`` and list of dplls registered in the subsystem
517 of parent dplls, targeted by ``DPLL_A_PIN_PARENT_ID`` attribute which is
/linux/drivers/ata/
H A Dpata_hpt3x2n.c92 * different DPLLs