| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_dpll.c | 142 * Context: Called under pf->dplls.lock
194 * Context: Acquires pf->dplls.lock
214 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_set()
216 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_set()
232 * Context: Calls a function which acquires pf->dplls.lock
257 * Context: Calls a function which acquires pf->dplls.lock
283 * Context: Acquires pf->dplls.lock
298 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_get()
300 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_get()
316 * Context: Calls a function which acquires pf->dplls.lock
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| H A D | ice_dpll.h | 109 * @clock_id: clock_id of dplls
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| H A D | ice.h | 516 ICE_FLAG_DPLL, /* SyncE/PTP dplls initialized */
661 struct ice_dplls dplls; member
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| /linux/drivers/dpll/zl3073x/ |
| H A D | devlink.c | 94 /* Unregister all DPLLs */ in zl3073x_devlink_reload_down()
95 list_for_each_entry(zldpll, &zldev->dplls, list) in zl3073x_devlink_reload_down()
128 /* Re-register all DPLLs */ in zl3073x_devlink_reload_up()
129 list_for_each_entry(zldpll, &zldev->dplls, list) { in zl3073x_devlink_reload_up()
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| H A D | core.c | 804 list_for_each_entry(zldpll, &zldev->dplls, list) in zl3073x_dev_periodic_work()
824 /* Release DPLLs */ in zl3073x_dev_dpll_fini()
825 list_for_each_entry_safe(zldpll, next, &zldev->dplls, list) { in zl3073x_dev_dpll_fini()
840 INIT_LIST_HEAD(&zldev->dplls); in zl3073x_devm_dpll_init()
842 /* Initialize all DPLLs */ in zl3073x_devm_dpll_init()
860 list_add_tail(&zldpll->list, &zldev->dplls); in zl3073x_devm_dpll_init()
901 * and enable DPLL-to-its-ref phase measurement for all DPLLs.
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| H A D | core.h | 74 * @dplls: list of DPLLs
90 struct list_head dplls; member
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| /linux/arch/arm/mach-omap2/ |
| H A D | clock.c | 85 /* Fint setup for DPLLs */ in ti_clk_init_features()
96 /* Bypass value setup for DPLLs */ in ti_clk_init_features()
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| H A D | cm2xxx.c | 24 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
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| /linux/include/linux/clk/ |
| H A D | ti.h | 75 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
79 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
161 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
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| /linux/Documentation/devicetree/bindings/dpll/ |
| H A D | dpll-device.yaml | 15 have one or more channels (DPLLs) and one or more physical input and
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_lvds_regs.h | 14 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
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| H A D | intel_ddi.c | 4400 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", in intel_ddi_initial_fastset_check()
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| /linux/drivers/dpll/ |
| H A D | dpll_core.h | 45 * @dpll_refs: hold referencees to dplls pin was registered with
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| H A D | dpll_core.c | 724 * between newly registered pin and dplls connected with a parent pin.
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| /linux/drivers/clk/ti/ |
| H A D | clkt_dpll.c | 228 * DPLLs can be locked or bypassed - basically, enabled or disabled.
231 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
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| H A D | dpll3xxx.c | 420 /* Configure dco and sd_div for dplls that have these fields */ in omap3_noncore_dpll_program()
506 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | psb_intel_display.c | 225 /* The LVDS pin pair needs to be on before the DPLLs are enabled. in psb_intel_crtc_mode_set()
239 * set the DPLLs for dual-channel mode or not. in psb_intel_crtc_mode_set()
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| H A D | cdv_intel_display.c | 730 /* The LVDS pin pair needs to be on before the DPLLs are enabled. in cdv_intel_crtc_mode_set()
742 * set the DPLLs for dual-channel mode or not. in cdv_intel_crtc_mode_set()
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| H A D | psb_intel_reg.h | 438 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
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| /linux/Documentation/driver-api/ |
| H A D | dpll.rst | 36 ``DPLL_CMD_DEVICE_GET`` and list of dplls registered in the subsystem
441 of parent dplls, targeted by ``DPLL_A_PIN_PARENT_ID`` attribute which is
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | dm814x-clocks.dtsi | 5 * See TRM "2.6.10 Connected outputso DPLLS" and
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| /linux/drivers/ata/ |
| H A D | pata_hpt3x2n.c | 92 * different DPLLs
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