| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn301/ |
| H A D | dcn301_dio_link_encoder.c | 124 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn301_link_encoder_construct()
129 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn301_link_encoder_construct()
130 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn301_link_encoder_construct()
131 * By this, adding DIGG should not hurt DCE 8.0. in dcn301_link_encoder_construct()
132 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn301_link_encoder_construct()
174 /* Override features with DCE-specific values */ in dcn301_link_encoder_construct()
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| /linux/include/uapi/linux/hdlc/ |
| H A D | ioctl.h | 10 #define CLOCK_INT 2 /* Internal TX and RX clock - DCE */
65 unsigned short dce; /* 1 for DCE (network side) operation */ member
83 unsigned short dce; /* 1 for DCE (network side) operation */ member
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_link_encoder.c | 156 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn201_link_encoder_construct()
161 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn201_link_encoder_construct()
162 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn201_link_encoder_construct()
163 * By this, adding DIGG should not hurt DCE 8.0. in dcn201_link_encoder_construct()
164 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn201_link_encoder_construct()
191 /* Override features with DCE-specific values */ in dcn201_link_encoder_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | Makefile | 23 # Makefile for common 'dce' logic
29 DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o \ macro
35 AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
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| H A D | dce_clk_mgr.c | 54 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
202 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS in get_max_pixel_clock_for_all_paths()
227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
464 * the dce clock manager. This operation will overwrite the existing dprefclk
619 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
623 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
625 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
627 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
[all …]
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| H A D | dce_link_encoder.c | 36 #include "dce/dce_11_0_d.h"
37 #include "dce/dce_11_0_sh_mask.h"
38 #include "dce/dce_11_0_enum.h"
657 /*In DCE 11, we are able to pre-program a Force SR register in dce110_psr_program_dp_dphy_fast_training()
850 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dce110_link_encoder_construct()
855 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dce110_link_encoder_construct()
856 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dce110_link_encoder_construct()
857 * By this, adding DIGG should not hurt DCE 8.0. in dce110_link_encoder_construct()
858 * This will let DCE 8.1 share DCE 8.0 as much as possible in dce110_link_encoder_construct()
898 /* Override features with DCE-specific values */ in dce110_link_encoder_construct()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| H A D | dcn30_dio_link_encoder.c | 135 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn30_link_encoder_construct()
140 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn30_link_encoder_construct()
141 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn30_link_encoder_construct()
142 * By this, adding DIGG should not hurt DCE 8.0. in dcn30_link_encoder_construct()
143 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn30_link_encoder_construct()
185 /* Override features with DCE-specific values */ in dcn30_link_encoder_construct()
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-led-trigger-tty | 29 DCE is ready to accept data from the DTE.
39 DCE is ready to receive and send data.
49 DTE is receiving a carrier from the DCE.
59 DCE has detected an incoming ring signal on the telephone
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_link_encoder.c | 376 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn21_link_encoder_construct()
381 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn21_link_encoder_construct()
382 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn21_link_encoder_construct()
383 * By this, adding DIGG should not hurt DCE 8.0. in dcn21_link_encoder_construct()
384 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn21_link_encoder_construct()
426 /* Override features with DCE-specific values */ in dcn21_link_encoder_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_opp_v.c | 29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
32 #include "dce/dce_opp.h"
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| H A D | dce60_resource.c | 28 #include "dce/dce_6_0_d.h"
29 #include "dce/dce_6_0_sh_mask.h"
43 #include "dce/dce_mem_input.h"
44 #include "dce/dce_link_encoder.h"
45 #include "dce/dce_stream_encoder.h"
46 #include "dce/dce_ipp.h"
47 #include "dce/dce_transform.h"
48 #include "dce/dce_opp.h"
49 #include "dce/dce_clock_source.h"
50 #include "dce/dce_audio.h"
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| /linux/drivers/net/wan/ |
| H A D | hdlc_fr.c | 11 DCE mode:
352 if (state(hdlc)->settings.dce) { in pvc_close()
462 int dce = state(hdlc)->settings.dce; in fr_lmi_send() local
468 if (dce && fullrep) { in fr_lmi_send()
489 data[i++] = dce ? LMI_STATUS : LMI_STATUS_ENQUIRY; in fr_lmi_send()
502 if (dce && fullrep) { in fr_lmi_send()
575 if (!state(hdlc)->settings.dce) in fr_set_link_state()
590 if (state(hdlc)->settings.dce) { in fr_timer()
615 if (state(hdlc)->settings.dce) { in fr_timer()
639 int dce = state(hdlc)->settings.dce; in fr_lmi_recv() local
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| H A D | hdlc_x25.c | 202 if (state(hdlc)->settings.dce) in x25_open()
307 new_settings.dce = 0; in x25_ioctl()
317 if ((new_settings.dce != 0 && in x25_ioctl()
318 new_settings.dce != 1) || in x25_ioctl()
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| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/ |
| H A D | dcn20_link_encoder.c | 435 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn20_link_encoder_construct()
440 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn20_link_encoder_construct()
441 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn20_link_encoder_construct()
442 * By this, adding DIGG should not hurt DCE 8.0. in dcn20_link_encoder_construct()
443 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn20_link_encoder_construct()
485 /* Override features with DCE-specific values */ in dcn20_link_encoder_construct()
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| /linux/Documentation/filesystems/smb/ |
| H A D | ksmbd.rst | 15 performance in userspace. So, DCE/RPC management that has historically resulted
34 currently DCE/RPC commands are identified to be handled through the user space.
59 NetServerGetInfo. Complete DCE/RPC response is prepared from the user space
104 DCE/RPC support Partially Supported. a few calls(NetShareEnumAll,
110 DCE/RPC management calls (and future support
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| /linux/drivers/gpu/drm/amd/display/dc/dce112/ |
| H A D | dce112_compressor.c | 28 #include "dce/dce_11_2_d.h"
29 #include "dce/dce_11_2_sh_mask.h"
677 * Use Channel 0 & 1 / Not used for DCE 11 */ in dce112_compressor_program_lpt_control()
679 /*Use Channel 0 for LPT for DCE 11 */ in dce112_compressor_program_lpt_control()
727 * DCE 11 Frame Buffer Compression Implementation
735 * for DCE 11 regions cannot be used - does not work with S/G in dce112_compressor_set_fbc_invalidation_triggers()
749 * For DCE 11 CSM metadata 11111 means - "Not Compressed" in dce112_compressor_set_fbc_invalidation_triggers()
796 /* For DCE 11 always use one DRAM channel for LPT */ in dce112_compressor_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/bios/ |
| H A D | Makefile | 35 # DCE 6x
44 # DCE 8x
51 # DCE 11x
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | smu7_common.h | 43 #include "dce/dce_10_0_d.h"
44 #include "dce/dce_10_0_sh_mask.h"
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| /linux/Documentation/devicetree/bindings/arm/tegra/ |
| H A D | nvidia,tegra234-cbb.yaml | 17 which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and
48 - nvidia,tegra234-dce-fabric
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/ |
| H A D | Makefile | 34 # DCE 6x
46 # DCE 8x
56 # DCE 11x
65 # DCE 12x
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| H A D | dce112_clk_mgr.c | 29 #include "dce/dce_11_2_d.h"
30 #include "dce/dce_11_2_sh_mask.h"
197 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| H A D | Makefile | 35 # DCE 60
45 # DCE 100 and DCE8x
54 # DCE 100 and DCE8x
62 # DCE 112
70 # DCE 120
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce112/ |
| H A D | dce112_hwseq.c | 34 #include "dce/dce_11_2_d.h"
35 #include "dce/dce_11_2_sh_mask.h"
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| /linux/lib/ |
| H A D | uuid.c | 38 /* Set the UUID variant to DCE */ in generate_random_uuid()
48 /* Set the GUID variant to DCE */ in generate_random_guid()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce80/ |
| H A D | hw_factory_dce80.c | 37 #include "dce/dce_8_0_d.h"
38 #include "dce/dce_8_0_sh_mask.h"
|