Home
last modified time | relevance | path

Searched +full:d +full:- +full:phy (Results 1 – 25 of 1093) sorted by relevance

12345678910>>...44

/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
10 #include <dt-bindings/phy/phy.h>
14 #define S_DIV_ROUND_UP(n, d) \ argument
15 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
22 v = (tmax - tmin) * percent; in linear_inter()
25 return max_t(s32, min_result, v - 1); in linear_inter()
37 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
38 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
48 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
[all …]
/linux/drivers/scsi/libsas/
H A Dsas_init.c1 // SPDX-License-Identifier: GPL-2.0-only
32 spin_lock_init(&task->task_state_lock); in sas_alloc_task()
33 task->task_state_flags = SAS_TASK_STATE_PENDING; in sas_alloc_task()
51 task->slow_task = slow; in sas_alloc_slow_task()
52 slow->task = task; in sas_alloc_slow_task()
53 timer_setup(&slow->timer, NULL, 0); in sas_alloc_slow_task()
54 init_completion(&slow->completion); in sas_alloc_slow_task()
62 kfree(task->slow_task); in sas_free_task()
67 /*------------ SAS addr hash -----------*/
77 for (b = (SAS_ADDR_SIZE - 1); b >= 0; b--) { in sas_hash_addr()
[all …]
H A Dsas_port.c1 // SPDX-License-Identifier: GPL-2.0
15 static bool phy_is_wideport_member(struct asd_sas_port *port, struct asd_sas_phy *phy) in phy_is_wideport_member() argument
17 struct sas_ha_struct *sas_ha = phy->ha; in phy_is_wideport_member()
19 if (memcmp(port->attached_sas_addr, phy->attached_sas_addr, in phy_is_wideport_member()
20 SAS_ADDR_SIZE) != 0 || (sas_ha->strict_wide_ports && in phy_is_wideport_member()
21 memcmp(port->sas_addr, phy->sas_addr, SAS_ADDR_SIZE) != 0)) in phy_is_wideport_member()
26 static void sas_resume_port(struct asd_sas_phy *phy) in sas_resume_port() argument
29 struct asd_sas_port *port = phy->port; in sas_resume_port()
30 struct sas_ha_struct *sas_ha = phy->ha; in sas_resume_port()
31 struct sas_internal *si = to_sas_internal(sas_ha->shost->transportt); in sas_resume_port()
[all …]
/linux/drivers/scsi/aic94xx/
H A Daic94xx_scb.c1 // SPDX-License-Identifier: GPL-2.0-only
19 /* ---------- EMPTY SCB ---------- */
36 static void get_lrate_mode(struct asd_phy *phy, u8 oob_mode) in get_lrate_mode() argument
38 struct sas_phy *sas_phy = phy->sas_phy.phy; in get_lrate_mode()
43 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
44 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
47 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
48 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
51 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; in get_lrate_mode()
52 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; in get_lrate_mode()
[all …]
/linux/drivers/nfc/
H A Dmei_phy.c1 // SPDX-License-Identifier: GPL-2.0
74 16, 1, (skb)->data, (skb)->len, false); \
81 16, 1, (skb)->data, (skb)->len, false); \
87 pr_debug("cmd=%02d status=%d req_id=%d rsvd=%d size=%d\n", \
88 (_hdr)->cmd, (_hdr)->status, (_hdr)->req_id, \
89 (_hdr)->reserved, (_hdr)->data_size); \
92 static int mei_nfc_if_version(struct nfc_mei_phy *phy) in mei_nfc_if_version() argument
107 r = mei_cldev_send(phy->cldev, (u8 *)&cmd, sizeof(struct mei_nfc_cmd)); in mei_nfc_if_version()
119 return -ENOMEM; in mei_nfc_if_version()
121 bytes_recv = mei_cldev_recv(phy->cldev, (u8 *)reply, if_version_length); in mei_nfc_if_version()
[all …]
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
19 #include <linux/phy/phy.h>
22 #include <dt-bindings/firmware/imx/rsrc.h>
63 ((x) < 32) ? 0xe0 | ((x) - 16) : \
64 ((x) < 64) ? 0xc0 | ((x) - 32) : \
65 ((x) < 128) ? 0x80 | ((x) - 64) : \
66 ((x) - 128))
67 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
68 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dlo.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 G PHY LO (LocalOscillator) Measuring and Control routines
8 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
10 Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
33 list_for_each_entry(c, &lo->calib_list, list) { in b43_find_lo_calib()
34 if (!b43_compare_bbatt(&c->bbatt, bbatt)) in b43_find_lo_calib()
36 if (!b43_compare_rfatt(&c->rfatt, rfatt)) in b43_find_lo_calib()
44 /* Write the LocalOscillator Control (adjust) value-pair. */
47 struct b43_phy *phy = &dev->phy; in b43_lo_write() local
51 if (unlikely(abs(control->i) > 16 || abs(control->q) > 16)) { in b43_lo_write()
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-xsphy.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
17 #include <linux/phy/phy.h>
21 #include "phy-mtk-io.h"
23 /* u2 phy banks */
28 /* u3 phy shared banks */
32 /* u3 phy banks */
86 /* PHY switch between pcie/usb3/sgmii */
94 struct phy *phy; member
96 struct clk *ref_clk; /* reference clock of anolog phy */
[all …]
H A Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
18 #include <linux/phy/phy.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
29 /* u2 phy bank */
31 /* u3/pcie/sata phy banks */
35 /* version V2/V3 sub-banks offset base address */
37 /* u2 phy banks */
[all …]
/linux/drivers/phy/intel/
H A Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay eMMC PHY driver
14 #include <linux/phy/phy.h>
18 /* eMMC/SD/SDIO core/phy configuration registers */
53 static int keembay_emmc_phy_power(struct phy *phy, bool on_off) in keembay_emmc_phy_power() argument
55 struct keembay_emmc_phy *priv = phy_get_drvdata(phy); in keembay_emmc_phy_power()
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
[all …]
H A Dphy-intel-lgm-emmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel eMMC PHY driver
14 #include <linux/phy/phy.h>
18 /* eMMC phy register definitions */
51 static int intel_emmc_phy_power(struct phy *phy, bool on_off) in intel_emmc_phy_power() argument
53 struct intel_emmc_phy *priv = phy_get_drvdata(phy); in intel_emmc_phy_power()
64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
67 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
75 rate = clk_get_rate(priv->emmcclk); in intel_emmc_phy_power()
78 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); in intel_emmc_phy_power()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
65 static int aq100x_reset(struct cphy *phy, int wait) in aq100x_reset() argument
71 int err = t3_phy_reset(phy, MDIO_MMD_VEND1, 3000); in aq100x_reset()
74 CH_WARN(phy->adapter, "PHY%d: reset failed (0x%x).\n", in aq100x_reset()
75 phy->mdio.prtad, err); in aq100x_reset()
80 static int aq100x_intr_enable(struct cphy *phy) in aq100x_intr_enable() argument
82 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AQ_IMASK_PMA, IMASK_PMA); in aq100x_intr_enable()
86 err = t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, IMASK_GLOBAL); in aq100x_intr_enable()
[all …]
/linux/drivers/nfc/pn533/
H A Dusb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for NXP PN533 NFC Chip - USB transport layer
6 * Copyright (C) 2012-2013 Tieto Poland
61 struct pn533_usb_phy *phy = urb->context; in pn533_recv_response() local
64 if (!urb->status) { in pn533_recv_response()
65 skb = alloc_skb(urb->actual_length, GFP_ATOMIC); in pn533_recv_response()
67 nfc_err(&phy->udev->dev, "failed to alloc memory\n"); in pn533_recv_response()
69 skb_put_data(skb, urb->transfer_buffer, in pn533_recv_response()
70 urb->actual_length); in pn533_recv_response()
74 pn533_recv_frame(phy->priv, skb, urb->status); in pn533_recv_response()
[all …]
/linux/drivers/phy/cadence/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Cadence PHYs
7 tristate "Cadence Torrent PHY driver"
13 Support for Cadence Torrent PHY.
16 tristate "Cadence D-PHY Support"
21 Choose this option if you have a Cadence D-PHY in your
23 cdns-dphy.
26 tristate "Cadence D-PHY Rx Support"
31 Support for Cadence D-PHY in Rx configuration.
34 tristate "Cadence Sierra PHY Driver"
[all …]
/linux/drivers/phy/starfive/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for StarFive platforms
9 tristate "StarFive JH7110 D-PHY RX support"
14 Choose this option if you have a StarFive D-PHY in your
16 phy-jh7110-dphy-rx.ko.
19 tristate "StarFive JH7110 D-PHY TX Support"
24 Choose this option if you have a StarFive D-PHY TX in your
26 phy-jh7110-dphy-tx.ko.
29 tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
33 Enable this to support the StarFive PCIe 2.0 PHY,
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
[all …]
/linux/drivers/scsi/
H A Dscsi_transport_sas.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2006 Dell Inc.
13 * introduces two additional intermediate objects: The SAS PHY
14 * as represented by struct sas_phy defines an "outgoing" PHY on
15 * a SAS HBA or Expander, and the SAS remote PHY represented by
16 * struct sas_rphy defines an "incoming" PHY on a SAS Expander or
18 * underlying hardware for a PHY and a remote PHY is the exactly
53 #define to_sas_host_attrs(host) ((struct sas_host_attrs *)(host)->shost_data)
102 return -EINVAL; \
151 { SAS_PHY_DISABLED, "Phy disabled" },
[all …]
/linux/drivers/usb/phy/
H A Dphy-tegra-usb.c1 // SPDX-License-Identifier: GPL-2.0
221 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val) in set_pts() argument
223 void __iomem *base = phy->regs; in set_pts()
226 if (phy->soc_config->has_hostpc) { in set_pts()
240 static void set_phcd(struct tegra_usb_phy *phy, bool enable) in set_phcd() argument
242 void __iomem *base = phy->regs; in set_phcd()
245 if (phy->soc_config->has_hostpc) { in set_phcd()
262 static int utmip_pad_open(struct tegra_usb_phy *phy) in utmip_pad_open() argument
266 ret = clk_prepare_enable(phy->pad_clk); in utmip_pad_open()
268 dev_err(phy->u_phy.dev, in utmip_pad_open()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmarvell,armada-cp110-utmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell Armada CP110/CP115 UTMI PHY
11 - Konstantin Porotchkin <kostap@marvell.com>
17 The USB device controller can only be connected to a single UTMI PHY port
18 0.H----- USB HOST0
19 UTMI PHY0 --------/
20 0.D-----0
[all …]
H A Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Ddebugfs.c1 // SPDX-License-Identifier: ISC
11 mt76_wr(dev, dev->mt76.debugfs_reg, val); in mt7615_reg_set()
23 *val = mt76_rr(dev, dev->mt76.debugfs_reg); in mt7615_reg_get()
57 ret = mt76_connac_mcu_chip_config(&dev->mt76); in mt7615_config()
74 mt7615_mac_set_scs(&dev->phy, val); in mt7615_scs_set()
87 *val = dev->phy.scs_en; in mt7615_scs_get()
99 struct mt76_connac_pm *pm = &dev->pm; in mt7615_pm_set()
105 if (!mt7615_firmware_offload(dev) || mt76_is_usb(&dev->mt76)) in mt7615_pm_set()
106 return -EOPNOTSUPP; in mt7615_pm_set()
108 mutex_lock(&dev->mt76.mutex); in mt7615_pm_set()
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
41 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
43 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
44 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp151a-prtt1c.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp151a-prtt1l.dtsi"
14 clock_ksz9031: clock-ksz9031 {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <25000000>;
20 clock_sja1105: clock-sja1105 {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qusb2.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
15 #include <linux/phy/phy.h>
22 #include <dt-bindings/phy/phy-qcom-qusb2.h>
105 * if yes, then offset gives index in the reg-layout
123 /* set of registers with offsets different per-PHY */
298 /* true if PHY has PLL_TEST register to select clk_scheme */
304 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
307 /* true if PHY default clk scheme is single-ended */
397 "vdd", "vdda-pll", "vdda-phy-dpdm",
[all …]
/linux/net/mac80211/
H A Ddebugfs_sta.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2003-2005 Devicescape Software, Inc.
6 * Copyright 2013-2014 Intel Mobile Communications GmbH
8 * Copyright (C) 2018 - 2023 Intel Corporation
17 #include "driver-ops.h"
26 struct sta_info *sta = file->private_data; \
28 format_string, sta->fiel
[all...]

12345678910>>...44