/linux/Documentation/devicetree/bindings/arm/ |
H A D | arm,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linus.walleij@linaro.org> 13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided 18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual 20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual 22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference 28 - arm,cortex-a9-scu 29 - arm,cortex-a5-scu [all …]
|
H A D | arm,realview.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linus.walleij@linaro.org> 14 Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the 22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created 26 - const: arm,realview-eb 27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S 28 (HBI-0147) was created as a development board to test ARM TrustZone, 31 - const: arm,realview-pb1176 [all …]
|
/linux/arch/arm/boot/dts/calxeda/ |
H A D | highbank.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright 2011-2012 Calxeda, Inc. 6 /dts-v1/; 14 #address-cells = <1>; 15 #size-cells = <1>; 18 #address-cells = <1>; 19 #size-cells = <0>; 22 compatible = "arm,cortex-a9"; 25 next-level-cache = <&L2>; 27 clock-names = "cpu"; [all …]
|
/linux/arch/arm/boot/dts/arm/ |
H A D | vexpress-v2p-ca9.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 * Cortex-A9 MPCore (V2P-CA9) 8 * HBI-0191B 11 /dts-v1/; 12 #include "vexpress-v2m.dtsi" 15 model = "V2P-CA9"; 18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <1>; 21 #size-cells = <1>; [all …]
|
H A D | arm-realview-pbx-a9.dts | 23 /dts-v1/; 24 #include "arm-realview-pbx.dtsi" 28 * This is the RealView Platform Baseboard Explore for Cortex-A9 31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9"; 35 #address-cells = <1>; 36 #size-cells = <0>; 37 enable-method = "arm,realview-smp"; 39 cpu-map { 51 compatible = "arm,cortex-a9"; 53 next-level-cache = <&L2>; [all …]
|
H A D | arm-realview-eb-a9mp.dts | 23 /dts-v1/; 24 #include "arm-realview-eb-mp.dtsi" 27 model = "ARM RealView EB Cortex A9 MPCore"; 30 * This is the Cortex A9 MPCore tile used with the 34 #address-cells = <1>; 35 #size-cells = <0>; 36 enable-method = "arm,realview-smp"; 40 compatible = "arm,cortex-a9"; 42 next-level-cache = <&L2>; 47 compatible = "arm,cortex-a9"; [all …]
|
/linux/arch/arm/boot/dts/actions/ |
H A D | owl-s500.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * Copyright (c) 2016-2017 Andreas Färber 8 #include <dt-bindings/clock/actions,s500-cmu.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/power/owl-s500-powergate.h> 12 #include <dt-bindings/reset/actions,s500-reset.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; [all …]
|
/linux/arch/arm/mach-versatile/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 52 bool "Include support for Integrator/IM-PD1" 60 The IM-PD1 is an add-on logic module for the Integrator which 62 The IM-PD1 can be found on the Integrator/PP2 platform. 77 bool "Integrator/CM922T-XA10 core module" 83 bool "Integrator/CM926EJ-S core module" 107 bool "Integrator/CM1026EJ-S core module" 113 bool "Integrator/CM1136JF-S core module" 129 bool "Integrator/CT926 (ARM926EJ-S) core tile" 135 bool "Integrator/CTB36 (ARM1136JF-S) core tile" [all …]
|
/linux/Documentation/devicetree/bindings/arm/cpu-enable-method/ |
H A D | nuvoton,npcm750-smp | 2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding 5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be 8 Enable method name: "nuvoton,npcm750-smp" 10 Compatible CPUs: "arm,cortex-a9" 14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and 15 "nuvoton,npcm750-gcr". 20 #address-cells = <1>; 21 #size-cells = <0>; 22 enable-method = "nuvoton,npcm750-smp"; 26 compatible = "arm,cortex-a9"; [all …]
|
/linux/Documentation/devicetree/bindings/cpufreq/ |
H A D | cpufreq-dt.txt | 11 - None 14 - operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for 17 - clock-latency: Specify the possible maximum transition latency for clock, 19 - voltage-tolerance: Specify the CPU voltage tolerance in percentage. 20 - #cooling-cells: 22 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. 27 #address-cells = <1>; 28 #size-cells = <0>; 31 compatible = "arm,cortex-a9"; 33 next-level-cache = <&L2>; [all …]
|
/linux/Documentation/devicetree/bindings/timer/ |
H A D | arm,global_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Stuart Menefy <stuart.menefy@st.com> 13 Cortex-A9 are often associated with a per-core Global timer. 18 - enum: 19 - arm,cortex-a5-global-timer 20 - arm,cortex-a9-global-timer 34 - compatible 35 - reg [all …]
|
H A D | arm,twd-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ARM Timer-Watchdog Timer 10 - Rob Herring <robh@kernel.org> 13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core 14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer 17 The TWD is usually attached to a GIC to deliver its two per-processor 23 - arm,cortex-a9-twd-timer [all …]
|
/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm63138.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/interrupt-controller/irq.h> 10 #address-cells = <1>; 11 #size-cells = <1>; 14 interrupt-parent = <&gic>; 22 #address-cells = <1>; 23 #size-cells = <0>; 27 compatible = "arm,cortex-a9"; 28 next-level-cache = <&L2>; [all …]
|
H A D | bcm21664.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 4 #include "bcm2166x-common.dtsi" 7 interrupt-parent = <&gic>; 10 #address-cells = <1>; 11 #size-cells = <0>; 15 compatible = "arm,cortex-a9"; 21 compatible = "arm,cortex-a9"; 22 enable-method = "brcm,bcm11351-cpu-method"; 23 secondary-boot-reg = <0x35004178>; 30 gic: interrupt-controller@1c01000 { [all …]
|
H A D | bcm-hr2.dtsi | 33 #include <dt-bindings/interrupt-controller/arm-gic.h> 34 #include <dt-bindings/interrupt-controller/irq.h> 39 interrupt-parent = <&gic>; 40 #address-cells = <1>; 41 #size-cells = <1>; 44 #address-cells = <1>; 45 #size-cells = <0>; 49 compatible = "arm,cortex-a9"; 50 next-level-cache = <&L2>; 56 compatible = "arm,cortex-a9-pmu"; [all …]
|
/linux/arch/arm/mach-bcm/ |
H A D | bcm63xx_smp.c | 1 // SPDX-License-Identifier: GPL-2.0-only 22 /* Size of mapped Cortex A9 SCU address space */ 26 * Enable the Cortex A9 Snoop Control Unit 29 * cores present. We assume we're running on a Cortex A9 processor, 43 return -ENXIO; in scu_a9_enable() 50 return -ENOENT; in scu_a9_enable() 57 return -ENOMEM; in scu_a9_enable() 70 /* The BCM63138 SoC has two Cortex-A9 CPUs, CPU0 features a complete in scu_a9_enable() 72 * Since we will not be able to trap kernel-mode NEON to force in scu_a9_enable() 76 * all, for kernel-mode NEON, we do not want to introduce any in scu_a9_enable() [all …]
|
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 61 applications. The SoC features dual core Cortex A9 ARM CPUs, 63 Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and 146 can be disabled for an SMP-enabled kernel. 174 BCM53573 series is set of SoCs using ARM Cortex-A7 CPUs with wireless 196 Say Y if you intend to run the kernel on a Broadcom ARM-based STB 199 This enables support for Broadcom ARM-based set-top box chipsets, 209 Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based 212 This enables support for Broadcom BCA ARM-based broadband chipsets, 220 bool "Cortex-A7 SoCs" [all …]
|
/linux/arch/arm/boot/dts/nuvoton/ |
H A D | nuvoton-npcm730.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 #include "nuvoton-common-npcm7xx.dtsi" 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&gic>; 12 #address-cells = <1>; 13 #size-cells = <0>; 14 enable-method = "nuvoton,npcm750-smp"; 18 compatible = "arm,cortex-a9"; 20 clock-names = "clk_cpu"; [all …]
|
H A D | nuvoton-npcm750.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 #include "nuvoton-common-npcm7xx.dtsi" 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&gic>; 13 #address-cells = <1>; 14 #size-cells = <0>; 15 enable-method = "nuvoton,npcm750-smp"; 19 compatible = "arm,cortex-a9"; 21 clock-names = "clk_cpu"; [all …]
|
/linux/arch/arm/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 159 The ARM series is a line of low-power-consumption RISC chip designs 161 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 162 manufactured, but legacy ARM-based PC hardware remains popular in 173 supported in LLD until version 14. The combined range is -/+ 256 MiB, 266 Patch phys-to-virt and virt-to-phys translation functions at 270 This can only be used with non-XIP MMU kernels where the base 316 bool "MMU-based Paged Memory Management Support" 319 Select if you want MMU-based virtualised addressing space 354 # This is sorted alphabetically by mach-* pathname. However, plat-* [all …]
|
/linux/arch/arm/boot/dts/st/ |
H A D | spear13xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&gic>; 14 #address-cells = <1>; 15 #size-cells = <0>; 18 compatible = "arm,cortex-a9"; 21 next-level-cache = <&L2>; 25 compatible = "arm,cortex-a9"; 28 next-level-cache = <&L2>; [all …]
|
/linux/Documentation/devicetree/bindings/watchdog/ |
H A D | arm,twd-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ARM Timer-Watchdog Watchdog 10 - Rob Herring <robh@kernel.org> 13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core 14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer 17 The TWD is usually attached to a GIC to deliver its two per-processor 23 - arm,cortex-a9-twd-wdt [all …]
|
/linux/Documentation/devicetree/bindings/arm/ux500/ |
H A D | boards.txt | 1 ST-Ericsson Ux500 boards 2 ------------------------ 5 compatible = "st-ericsson,mop500" (legacy) 6 compatible = "st-ericsson,u8500" 10 soc: represents the system-on-chip and contains the chip 20 compatible = "ste,dbx500-backupram" 25 interrupt-controller: 26 see binding for interrupt-controller/arm,gic.txt 29 see binding for timer/arm,twd-timer.yaml 36 /dts-v1/; [all …]
|
/linux/arch/arm/boot/dts/nxp/vf/ |
H A D | vf500.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #address-cells = <1>; 10 #size-cells = <1>; 15 #address-cells = <1>; 16 #size-cells = <0>; 19 compatible = "arm,cortex-a5"; 28 intc: interrupt-controller@40003000 { 29 compatible = "arm,cortex-a9-gic"; 30 #interrupt-cells = <3>; [all …]
|
/linux/arch/arm/boot/dts/axis/ |
H A D | artpec6.dtsi | 2 * Device Tree Source for the Axis ARTPEC-6 SoC 4 * This file is dual-licensed: you can use it either under the terms 43 #include <dt-bindings/interrupt-controller/arm-gic.h> 44 #include <dt-bindings/dma/nbpfaxi.h> 45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h> 48 #address-cells = <1>; 49 #size-cells = <1>; 51 interrupt-parent = <&intc>; 54 #address-cells = <1>; 55 #size-cells = <0>; [all …]
|