| /linux/arch/arm64/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
279 ARM 64-bit (AArch64) Linux support.
287 # required due to use of the -Zfixed-x18 flag.
290 # -Zsanitizer=shadow-call-stack flag.
300 depends on $(cc-option,-fpatchable-function-entry=2)
326 # VA_BITS - PAGE_SHIFT - 3
404 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
409 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
455 A/D updates can occur after a PTE has been marked invalid.
459 at stage-2.
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| /linux/Documentation/devicetree/bindings/cpu/ |
| H A D | cpu-topology.txt | 6 1 - Introduction
9 In a SMP system, the hierarchy of CPUs is defined through three entities that
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
35 A topology description containing phandles to cpu nodes that are not compliant
[all …]
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| H A D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
21 representing the range of dynamic idle states that a processor can enter at
[all …]
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| H A D | cpu-capacity.txt | 6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
[all …]
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| /linux/Documentation/translations/zh_TW/arch/arm64/ |
| H A D | silicon-errata.txt | 1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
6 original document maintainer directly. However, if you have a problem
9 or if there is a problem with the translation.
15 ---------------------------------------------------------------------
16 Documentation/arch/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
41 A 類：無可行補救措施的嚴重缺陷。
50 情況下，爲將 A 類缺陷當作 C 類處理，可能需要用類似的手段。這些手段被
55 相應的內核配置（Kconfig）選項被加在 “內核特性（Kernel Features）”->
[all …]
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| /linux/Documentation/translations/zh_CN/arch/arm64/ |
| H A D | silicon-errata.txt | 1 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
4 original document maintainer directly. However, if you have a problem
7 or if there is a problem with the translation.
12 ---------------------------------------------------------------------
13 Documentation/arch/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
37 A 类：无可行补救措施的严重缺陷。
46 情况下，为将 A 类缺陷当作 C 类处理，可能需要用类似的手段。这些手段被
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,corstone1000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
11 - Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
15 provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
21 a secure SoC for a range of rich IoT applications, for example gateways, smart
[all …]
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| H A D | arm,realview.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
23 as a generic platform to test different FPGA designs, and has
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
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| H A D | arm,vexpress-juno.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
18 The board consist of a motherboard and one or more daughterboards (tiles). The
19 motherboard provides a set of peripherals. Processor and RAM "live" on the
22 The motherboard and each core tile should be described by a separate Device
[all …]
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| H A D | arm,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
14 with a Snoop Control Unit. The register range is usually 256 (0x100)
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
28 - arm,cortex-a9-scu
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|
| /linux/Documentation/arch/arm64/ |
| H A D | silicon-errata.rst | 10 so-called "errata", which can cause it to deviate from the architecture
15 Category A A critical error without a viable workaround.
16 Category B A significant or critical error with an acceptable
18 Category C A minor error that is not expected to occur under normal
27 treatment in the operating system. For example, avoiding a particular
28 sequence of code, or configuring the processor in a particular way. A
30 a Category A erratum into a Category C erratum. These are collectively
32 cases (e.g. those cases that both require a non-secure workaround *and*
36 the erratum in question, a Kconfig entry is added under "Kernel
37 Features" -> "ARM errata workarounds via the alternatives framework".
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| /linux/arch/arm/mach-versatile/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
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| /linux/arch/arm64/kernel/ |
| H A D | cpu_errata.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/arm-smccc.h>
24 if (!is_midr_in_range(midr, &entry->midr_range)) in is_affected_midr_range()
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) in is_affected_midr_range()
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mas in is_affected_midr_range()
[all...] |
| /linux/arch/arm/mm/ |
| H A D | proc-v7m.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
15 #include "proc-macros.S"
28 * Perform a soft reset of the system. Put the CPU into the
32 * - loc - location to jump to for soft reset
105 * This should be able to cover all ARMv7-M cores.
141 ldmia sp, {r0-r3, r12}
145 @ Special-purpose control register
151 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
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| H A D | proc-v7.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
15 #include <asm/asm-offsets.h>
17 #include <asm/pgtable-hwdef.h>
20 #include "proc-macros.S"
23 #include "proc-v7-3level.S"
25 #include "proc-v7-2level.S"
28 .arch armv7-a
45 * Perform a soft reset of the system. Put the CPU into the
[all …]
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| /linux/arch/arm/boot/dts/arm/ |
| H A D | arm-realview-eb-a9mp.dts | 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
27 model = "ARM RealView EB Cortex A9 MPCore";
30 * This is the Cortex A9 MPCore tile used with the
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "arm,realview-smp";
40 compatible = "arm,cortex-a9";
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| H A D | arm-realview-pbx-a9.dts | 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
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|
| /linux/drivers/soc/tegra/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
63 # 64-bit ARM SoCs
75 Tegra124's "4+1" Cortex-A15 CPU complex.
85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
86 cores in a switched configuration. It features a GPU of the Maxwell
88 and providing 256 CUDA cores. It supports hardware-accelerated en-
92 Besides the multimedia features it also comes with a variety of I/O
94 name only a few.
105 Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
[all …]
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| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | arm,twd-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Watchdog
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-wdt
[all …]
|
| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | arm,twd-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Timer
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-timer
[all …]
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| H A D | arm,global_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stuart Menefy <stuart.menefy@st.com>
13 Cortex-A9 are often associated with a per-core Global timer.
18 - enum:
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
34 - compatible
35 - reg
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-ls2088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a72-pmu";
25 compatible = "arm,cortex-a72";
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
35 compatible = "arm,cortex-a72";
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| H A D | fsl-ls2080a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57-pmu";
25 compatible = "arm,cortex-a57";
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
[all …]
|
| /linux/Documentation/arch/arm/ |
| H A D | marvell.rst | 8 for a particular SoC is available in the Linux kernel. This document
13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
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| /linux/Documentation/devicetree/bindings/cpufreq/ |
| H A D | cpufreq-mediatek.txt | 5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
30 - #cooling-cells:
[all …]
|