| /linux/Documentation/translations/zh_TW/arch/arm64/ |
| H A D | silicon-errata.txt | 1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
6 original document maintainer directly. However, if you have a problem
9 or if there is a problem with the translation.
15 ---------------------------------------------------------------------
16 Documentation/arch/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
41 A 類：無可行補救措施的嚴重缺陷。
50 情況下，爲將 A 類缺陷當作 C 類處理，可能需要用類似的手段。這些手段被
55 相應的內核配置（Kconfig）選項被加在 “內核特性（Kernel Features）”->
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| /linux/Documentation/translations/zh_CN/arch/arm64/ |
| H A D | silicon-errata.txt | 1 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
4 original document maintainer directly. However, if you have a problem
7 or if there is a problem with the translation.
12 ---------------------------------------------------------------------
13 Documentation/arch/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
37 A 类：无可行补救措施的严重缺陷。
46 情况下，为将 A 类缺陷当作 C 类处理，可能需要用类似的手段。这些手段被
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,realview.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
14 Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
23 as a generic platform to test different FPGA designs, and has
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
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| H A D | arm,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
14 with a Snoop Control Unit. The register range is usually 256 (0x100)
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
28 - arm,cortex-a9-scu
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| H A D | actions.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Färber <afaerber@suse.de>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
19 - items:
20 - enum:
21 - allo,sparky # Allo.com Sparky
22 - cubietech,cubieboard6 # Cubietech CubieBoard6
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| /linux/arch/arm/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
50 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de
168 The ARM series is a line of low-power-consumption RISC chip designs
170 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
171 manufactured, but legacy ARM-based PC hardware remains popular in
172 Europe. There is an ARM Linux project with a web page at
179 relocations. The combined range is -/+ 256 MiB, which is usually
196 size. This works well for buffers up to a few hundreds kilobytes, but
197 for larger buffers it just a waste of address space. Drivers which has
199 virtual space with just a few allocations.
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| /linux/arch/arm/boot/dts/arm/ |
| H A D | arm-realview-eb-a9mp.dts | 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
27 model = "ARM RealView EB Cortex A9 MPCore";
30 * This is the Cortex A9 MPCore tile used with the
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "arm,realview-smp";
40 compatible = "arm,cortex-a9";
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| H A D | arm-realview-pbx-a9.dts | 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
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| /linux/arch/arm/mm/ |
| H A D | proc-v7m.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
15 #include "proc-macros.S"
28 * Perform a soft reset of the system. Put the CPU into the
32 * - loc - location to jump to for soft reset
105 * This should be able to cover all ARMv7-M cores.
141 ldmia sp, {r0-r3, r12}
145 @ Special-purpose control register
151 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
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| H A D | proc-v7.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
15 #include <asm/asm-offsets.h>
17 #include <asm/pgtable-hwdef.h>
20 #include "proc-macros.S"
23 #include "proc-v7-3level.S"
25 #include "proc-v7-2level.S"
28 .arch armv7-a
45 * Perform a soft reset of the system. Put the CPU into the
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| /linux/drivers/firmware/imx/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 It acts like a doorbell. Client might use shared memory to
18 The System Controller Firmware (SCFW) is a low-level system function
19 which runs on a dedicated Cortex-M core to provide power, clock, and
32 a low-level system function which runs on a dedicated Cortex-M
35 This driver can also be built as a module.
43 a low-level system function which runs on a dedicated Cortex-M
46 This driver can also be built as a module.
54 a low-level system function which runs on a dedicated Cortex-M
57 This driver can also be built as a module.
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| /linux/arch/arm64/kernel/ |
| H A D | cpu_errata.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/arm-smccc.h>
36 return midr_is_cpu_model_range(read_cpuid_id(), range->model, in is_midr_in_range()
37 range->rv_min, range->rv_max); in is_midr_in_range()
41 range->model, in is_midr_in_range()
42 range->rv_min, range->rv_max)) in is_midr_in_range()
50 while (ranges->model) in is_midr_in_range_list()
62 if (!is_midr_in_range(&entry->midr_range)) in __is_affected_midr_range()
66 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) in __is_affected_midr_range()
67 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) in __is_affected_midr_range()
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| /linux/Documentation/devicetree/bindings/cpu/ |
| H A D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
21 representing the range of dynamic idle states that a processor can enter at
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| H A D | cpu-capacity.txt | 6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
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| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | arm,twd-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Watchdog
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-wdt
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-ls2088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a72-pmu";
25 compatible = "arm,cortex-a72";
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
35 compatible = "arm,cortex-a72";
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| H A D | fsl-ls2080a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57-pmu";
25 compatible = "arm,cortex-a57";
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
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| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | arm,global_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stuart Menefy <stuart.menefy@st.com>
13 Cortex-A9 are often associated with a per-core Global timer.
18 - enum:
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
34 - compatible
35 - reg
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| /linux/Documentation/arch/arm/ |
| H A D | marvell.rst | 8 for a particular SoC is available in the Linux kernel. This document
13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
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| H A D | microchip.rst | 7 ------------
11 It is important to note that the Microchip (previously Atmel) ARM-based MPU
15 git branches/tags and email subject always contain this "at91" sub-string.
19 ---------
25 - at91rm9200
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-1768-32-bit-ARM920T-Embedded-Microprocessor-…
32 - at91sam9260
36 …ttp://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6221-32-bit-ARM926EJ-S-Embedded-Microprocesso…
38 - at91sam9xe
42 …ttp://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocesso…
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| /linux/Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| H A D | al,alpine-smp | 2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
6 enabling secondary CPUs. To apply to all CPUs, a single
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set for the device
33 #address-cells = <1>;
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| H A D | nuvoton,npcm750-smp | 2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
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| /linux/arch/arm/mach-bcm/ |
| H A D | bcm63xx_smp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 /* Size of mapped Cortex A9 SCU address space */
26 * Enable the Cortex A9 Snoop Control Unit
29 * cores present. We assume we're running on a Cortex A9 processor,
31 * SCU base is a problem.
43 return -ENXIO; in scu_a9_enable()
50 return -ENOENT; in scu_a9_enable()
57 return -ENOMEM; in scu_a9_enable()
70 /* The BCM63138 SoC has two Cortex-A9 CPUs, CPU0 features a complete in scu_a9_enable()
72 * Since we will not be able to trap kernel-mode NEON to force in scu_a9_enable()
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| /linux/arch/arm/boot/dts/amazon/ |
| H A D | alpine.dtsi | 22 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
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| /linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hip07.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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