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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A D	st,stm32-fmc2-nand.yaml	`41 $ref: raw-nand-chip.yaml 64 - description: Chip select 0 data 65 - description: Chip select 0 command 66 - description: Chip select 0 address space 67 - description: Chip select 1 data 68 - description: Chip select 1 command 69 - description: Chip select 1 address space 89 - description: Chip select 0 data 90 - description: Chip select 0 command 91 - description: Chip select 0 address space [all …]`
H A D	fsl-upm-nand.txt	5 - reg : should specify localbus chip select and size used for the chip. 10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support. 11 The corresponding address lines are used to select the chip. 13 (R/B#). For multi-chip devices, "n" GPIO definitions are required 17 - fsl,upm-wait-flags : add chip-dependent short delays after running the 20 - chip-delay : chip dependent delay for transferring data from array to 24 Each flash chip described may optionally contain additional sub-nodes 55 /* Multi-chip NAND device */
H A D	jedec,spi-nor.txt	`7 manufacturer and name of the chip. A list of supported chip 12 Supported chip names: 50 The following chip names have been used historically to 63 - reg : Chip-Select number 64 - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at 67 - m25p,fast-read : Use the "fast read" opcode to read data from the chip instead 71 by your chip.`
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/
H A D	frontend.json	71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru… 72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 89 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), … 90 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), … 95 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 96 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di… 102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d… 107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on … 108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on… [all …]
H A D	memory.json	5 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 6 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 11 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand … 12 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa… 23 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a… 24 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to … 35 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No… 36 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on the same N… [all …]
H A D	marked.json	35 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), … 41 …eload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), … 47 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 53 … reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 59 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 65 …"BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Gr… 71 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 77 …"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or G… 215 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to… 221 …"BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked l… [all …]
H A D	cache.json	5 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), … 6 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), … 11 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 12 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen… 101 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to… 102 …"PublicDescription": "The processor's data cache was reloaded from the local chip's L4 cache due t… 107 …d either shared or modified data from another core's L2/L3 on a different chip (remote or distant)… 108 …d either shared or modified data from another core's L2/L3 on a different chip (remote or distant)… [all …]
H A D	other.json	23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 36 … got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump w… 41 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a… 42 …urced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump w… 65 …ump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the origi… 66 …(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group… 71 …"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group… 72 …ope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all d… 377 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for either de… [all …]
H A D	translation.json	29 …e TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), … 35 …the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 89 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due… 95 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due t… 107 …B either shared or modified data from another core's L2/L3 on a different chip (remote or distant)… 113 … TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side … 119 …the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as… 125 …o the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as… 131 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…
/freebsd/sys/contrib/dev/rtw88/
H A D	coex.h	330 const struct rtw_chip_info chip = rtwdev->chip; in rtw_coex_set_init() local 332 chip->ops->coex_set_init(rtwdev); in rtw_coex_set_init() 338 const struct rtw_chip_info chip = rtwdev->chip; in rtw_coex_set_ant_switch() local 340 if (!chip->ops->coex_set_ant_switch) in rtw_coex_set_ant_switch() 343 chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type); in rtw_coex_set_ant_switch() 348 const struct rtw_chip_info chip = rtwdev->chip; in rtw_coex_set_gnt_fix() local 350 chip->ops->coex_set_gnt_fix(rtwdev); in rtw_coex_set_gnt_fix() 355 const struct rtw_chip_info chip = rtwdev->chip; in rtw_coex_set_gnt_debug() local 357 chip->ops->coex_set_gnt_debug(rtwdev); in rtw_coex_set_gnt_debug() 362 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_rfe_type() local [all …]
H A D	phy.c	126 struct rtw_hw_reg_offset edcca_th = rtwdev->chip->edcca_th; in rtw_phy_set_edcca_th() 141 const struct rtw_chip_info chip = rtwdev->chip; in rtw_phy_adaptivity_set_mode() local 154 dm_info->l2h_th_ini = chip->l2h_th_ini_ad; in rtw_phy_adaptivity_set_mode() 158 dm_info->l2h_th_ini = chip->l2h_th_ini_cs; in rtw_phy_adaptivity_set_mode() 168 const struct rtw_chip_info chip = rtwdev->chip; in rtw_phy_adaptivity_init() local 171 if (chip->ops->adaptivity_init) in rtw_phy_adaptivity_init() 172 chip->ops->adaptivity_init(rtwdev); in rtw_phy_adaptivity_init() 177 if (rtwdev->chip in rtw_phy_adaptivity() 183 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_cfo_init() local 202 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_init() local 229 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_dig_write() local 248 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_stat_false_alarm() local 606 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_dpk_track() local 662 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_cfo_track() local 723 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_cck_pd() local 898 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_read_rf() local 921 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_read_rf_sipi() local 970 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_write_rf_reg_sipi() local 1010 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_write_rf_reg() local 1745 const struct rtw_chip_info chip = rtwdev->chip; rtw_load_rfk_table() local 1764 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_load_tables() local 1873 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_get_dis_dpd_by_rate_diff() local 1907 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_get_2g_tx_power_index() local 1954 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_get_5g_tx_power_index() local 2207 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_set_tx_power_level() local 2482 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_set_tx_path_by_reg() local 2537 const struct rtw_chip_info chip = rtwdev->chip; rtw_phy_tx_path_diversity() local [all...]
H A D	coex.c	16 const struct rtw_chip_info chip = rtwdev->chip; in rtw_coex_next_rssi_state() local 17 u8 tol = chip->rssi_tolerance; in rtw_coex_next_rssi_state() 39 const struct rtw_chip_info chip = rtwdev->chip; in rtw_coex_limited_tx() local 44 if (!chip->scbd_support) in rtw_coex_limited_tx() 368 const struct rtw_chip_info chip = rtwdev->chip; in rtw_coex_write_scbd() local 373 if (!chip->scbd_support) in rtw_coex_write_scbd() 381 if (!chip in rtw_coex_write_scbd() 403 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_read_scbd() local 413 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_check_rfk() local 492 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_monitor_bt_enable() local 527 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_update_wl_link_info() local 708 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_update_bt_link_info() local 808 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_update_wl_ch_info() local 935 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_coex_ctrl_owner() local 983 const struct rtw_chip_info chip = rtwdev->chip; rtw_btc_wltoggle_table_a() local 1067 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_table() local 1137 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_set_tdma() local 1195 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_tdma() local 1528 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_coex_all_off() local 1551 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_freerun() local 1596 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_rf4ce() local 1621 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_whql_test() local 1646 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_relink() local 1686 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_idle() local 1755 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_inquiry() local 1855 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_game_hid() local 1903 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_hfp() local 1934 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_hid() local 2017 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_a2dp() local 2059 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_a2dpsink() local 2098 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_pan() local 2135 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_a2dp_hid() local 2192 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_a2dp_pan() local 2249 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_pan_hid() local 2284 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_bt_a2dp_pan_hid() local 2318 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_wl_under5g() local 2350 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_wl_only() local 2374 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_wl_native_lps() local 2413 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_wl_linkscan() local 2453 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_action_wl_not_connected() local 2530 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_run_coex() local 3004 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_bt_info_notify() local 3272 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_bt_hid_info_notify() local 3362 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_query_bt_hid_list() local 3584 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_get_table_index() local 3620 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_get_tdma_index() local 3738 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_set_coexinfo_hw() local 3912 const struct rtw_chip_info chip = rtwdev->chip; rtw_coex_display_coex_info() local [all...]
H A D	mac.c	169 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) in rtw_pwr_cmd_polling() 173 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) in rtw_pwr_cmd_polling() 273 const struct rtw_chip_info chip = rtwdev->chip; in rtw_mac_power_switch() local 309 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; in rtw_mac_power_switch() 313 if (chip->id == RTW_CHIP_TYPE_8822C \|\| in rtw_mac_power_switch() 314 chip->id == RTW_CHIP_TYPE_8822B \|\| in rtw_mac_power_switch() 315 chip->id == RTW_CHIP_TYPE_8821C) in rtw_mac_power_switch() 330 u8 sys_func_en = rtwdev->chip in __rtw_mac_init_system_cfg() 640 const struct rtw_chip_info chip = rtwdev->chip; download_firmware_to_mem() local 1005 const struct rtw_chip_info chip = rtwdev->chip; __rtw_mac_flush_prio_queue() local 1067 const struct rtw_chip_info chip = rtwdev->chip; txdma_queue_mapping() local 1118 const struct rtw_chip_info chip = rtwdev->chip; set_trx_fifo_info() local 1173 const struct rtw_chip_info chip = rtwdev->chip; __priority_queue_cfg() local 1204 const struct rtw_chip_info chip = rtwdev->chip; __priority_queue_cfg_legacy() local 1230 const struct rtw_chip_info chip = rtwdev->chip; priority_queue_cfg() local 1361 const struct rtw_chip_info *chip = rtwdev->chip; rtw_mac_init() local [all...]
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A D	translation.json	15 …ache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand loa… 25 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the … 35 …o the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as… 60 …the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 75 … TLB either shared or modified data from another core's L2/L3 on the same chip due to a instructio… 80 …ache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instructi… 95 …he was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand loa… 100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same… 135 … reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as… 150 …B either shared or modified data from another core's L2/L3 on a different chip (remote or distant)… [all …]
H A D	marked.json	20 …aded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side … 25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 30 …"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or mem… 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due… 70 … into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked dat… 95 …nto the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked dat… 100 … into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side … 120 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on … 130 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a… 145 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a… [all …]
H A D	pipeline.json	30 …aded either shared or modified data from another core's L2/L3 on the same chip due to a marked loa… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ… 80 …ed into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked dat… 90 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 95 …ed into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side … 135 …"BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L… 160 …B either shared or modified data from another core's L2/L3 on a different chip (remote or distant)… 190 …eloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as… 195 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 235 …eloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as… [all …]
/freebsd/contrib/ofed/libcxgb4/
H A D	t4_chip_type.h	41 /* We code the Chelsio T4 Family "Chip Code" as a tuple: 43 * (Chip Version, Chip Revision) 47 * Chip Version: is T4, T5, etc. 48 * Chip Revision: is the FAB "spin" of the Chip Version. 70 static inline int is_t4(enum chip_type chip) in is_t4() argument 72 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4); in is_t4() 75 static inline int is_t5(enum chip_type chip) in is_t5() argument 77 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); in is_t5() 80 static inline int is_t6(enum chip_type chip) in is_t6() argument 82 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6); in is_t6()
/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A D	mediatek,disp.txt	29 - compatible: "mediatek,<chip>-disp-<function>", one of 30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc) 31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc) 32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer 33 "mediatek,<chip>-disp-wdma" - write DMA 34 "mediatek,<chip>-disp-ccorr" - color correction 35 "mediatek,<chip>-disp-color" - color processor 36 "mediatek,<chip>-disp-dither" - dither 37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller 38 "mediatek,<chip>-disp-gamma" - gamma correction [all …]
/freebsd/share/man/man4/
H A D	ahc.4	`78 many chip-down motherboard configurations. 86 by a particular chip, may be disabled in a particular motherboard or card 90 .It Em "Chip" Ta "MIPS" Ta "Bus" Ta "MaxSync" Ta "MaxWidth" Ta "SCBs" Ta "Features" 110 Multi-function Twin Channel Device - Two controllers on one chip. 140 the chip for memory mapped I/O. The typical symptom of this problem is a 185 host adapter chip 189 host adapter chip 193 host adapter chip 197 host adapter chip 201 host adapter chip [all …]`
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A D	spi-sprd-adi.txt	4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI 9 48 hardware channels to access analog chip. For 2 software read/write channels, 10 users should set ADI registers to access analog chip. For hardware channels, 12 which means we can just link one analog chip address to one hardware channel, 13 then users can access the mapped analog chip address by this hardware channel 19 the analog chip address where user want to access by hardware components. 21 Since we have multi-subsystems will use unique ADI to access analog chip, when 36 - #address-cells: Number of cells required to define a chip select address 38 - #size-cells: Size of cells required to define a chip select address size 48 value specifies the analog chip address where user want to access
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	89 "BriefDescription": "L1D On-Chip L3 Sourced Writes", 90 …Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache witho… 95 "BriefDescription": "L1D Off-Chip L3 Sourced Writes", 96 …ata cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cac… 125 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", 126 … Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with … 131 "BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention", 132 …ata cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cac… 143 "BriefDescription": "L1I On-Chip L3 Sourced Writes", 144 …tion cache directory where the returned cache line was sourced from an On Chip Level-3 cache witho… [all …]
/freebsd/sys/dev/wbwd/
H A D	wbwd.c	`100 enum chips chip; member 117 * register as these might be different by chip. 126 enum chips chip; member 131 .chip = w83627hf, 136 .chip = w83627s, 141 .chip = w83697hf, 146 .chip = w83697ug, 151 .chip = w83637hf, 156 .chip = w83627thf, 161 .chip = w83687thf, [all …]`
/freebsd/sys/contrib/device-tree/Bindings/mips/cavium/
H A D	bootbus.txt	3 The Octeon Boot Bus is a configurable parallel bus with 8 chip 4 selects. Each chip select is independently configurable. 13 - #address-cells: Must be <2>. The first cell is the chip select 14 within the bootbus. The second cell is the offset from the chip select. 19 parent-bus-address, length) for each active chip select. If the 20 length element for any triplet is zero, the chip select is disabled, 23 The configuration parameters for each chip select are stored in child 29 - cavium,cs-index: A single cell indicating the chip select that 60 the bus for this chip select. 72 /* The chip select number and offset */ [all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A D	ar5212_power.c	30 * If requested, force chip awake. 32 * Returns A_OK if chip is awake or successfully forced awake. 35 * There is a problem with the chip where sometimes it will not wake up. 50 * with the chip powered down the read returns 0xffffffff in ar5212SetPowerModeAwake() 66 OS_DELAY(10); /* Give chip the chance to awake / in ar5212SetPowerModeAwake() 92 If requested, force chip to sleep. 104 * fames. If request, set power mode of chip to 117 * the chip as well 134 setChip ? "set chip " : ""); in ar5212SetPowerMode() 160 * Return the current sleep mode of the chip [all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A D	arm,pl172.txt	17 - ranges: Must contain one or more chip select memory regions. 28 Child chip-select (cs) nodes contain the memory devices nodes connected to 44 - mpmc,cs: Chip select number. Indicates to the pl0172 driver 47 - mpmc,memory-width: Width of the chip select memory. Must be equal to 54 - mpmc,cs-active-high: Set chip select polarity to active high. 67 - mpmc,write-enable-delay: Delay from chip select assertion to write 70 - mpmc,output-enable-delay: Delay from chip select assertion to output 73 - mpmc,write-access-delay: Delay from chip select assertion to write 76 - mpmc,read-access-delay: Delay from chip select assertion to read 88 Example for pl172 with nor flash on chip select 0 shown below.

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