Searched full:channel0 (Results 1 – 25 of 32) sorted by relevance
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| /linux/Documentation/leds/ |
| H A D | leds-lp5521.rst | 57 - /sys/class/leds/lp5521:channel0/led_current - RW
58 - /sys/class/leds/lp5521:channel0/max_current - RO
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | fsl,imx8qxp-ldb.yaml | 24 have to be different. Channel0 outputs odd pixels and channel1 outputs
30 data. In split mode, channel0 outputs odd pixels and channel1 outputs even
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| H A D | fsl,imx8qxp-pixel-link.yaml | 103 /* from dc0 pixel combiner channel0 */
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| /linux/drivers/mfd/ |
| H A D | mxs-lradc.c | 57 DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH0_IRQ, "mxs-lradc-channel0"),
76 DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH0_IRQ, "mxs-lradc-channel0"),
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | white-hawk-common.dtsi | 31 channel0 {
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| H A D | rz-smarc-common.dtsi | 86 channel0 {
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| H A D | r8a77970-eagle.dts | 124 channel0 {
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| H A D | condor-common.dtsi | 107 channel0 {
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| H A D | gray-hawk-single.dtsi | 271 channel0 {
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| H A D | ebisu.dtsi | 344 channel0 {
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| H A D | r9a07g043.dtsi | 431 channel0 {
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| /linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | ti,palmas-gpadc.yaml | 44 ti,channel0-current-microamp:
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | fsl,imx8qm-lvds-phy.yaml | 37 Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
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| /linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr-channel.yaml | 110 lpddr-channel0 {
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| /linux/tools/virtio/virtio-trace/ |
| H A D | README | 61 id=channel0,name=agent-ctl-path\
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| /linux/drivers/clocksource/ |
| H A D | timer-imx-tpm.c | 217 * 4) Channel0 disabled in tpm_timer_init()
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| /linux/arch/arm/mach-spear/ |
| H A D | time.c | 32 #define CLKEVT 0 /* gpt0, channel0 as clockevent */
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| /linux/drivers/media/platform/ti/davinci/ |
| H A D | vpif.h | 262 /* inline function to enable/disable channel0 */
280 /* inline function to enable interrupt for channel0 */
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| /linux/arch/arm/boot/dts/marvell/ |
| H A D | dove.dtsi | 327 channel0 {
347 channel0 {
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | umc_v6_7.c | 509 /* Enabling fatal error in umc instance0 channel0 will be in umc_v6_7_query_ras_poison_mode()
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap5-board-common.dtsi | 422 ti,channel0-current-microamp = <5>;
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| /linux/drivers/gpu/drm/msm/registers/display/ |
| H A D | mdp4.xml | 463 <bitfield name="CHANNEL0" pos="6" type="boolean"/>
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| /linux/include/uapi/linux/ |
| H A D | cdrom.h | 201 __u8 channel0; member
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| /linux/drivers/gpu/drm/bridge/ |
| H A D | tc358767.c | 297 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
298 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
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| /linux/drivers/dma/ |
| H A D | tegra186-gpc-dma.c | 166 /* Default channel mask reserving channel0 */
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