| /linux/drivers/net/ethernet/sfc/ |
| H A D | efx_channels.c | 156 * We need a channel per event queue, plus a VI per tx queue. in efx_allocate_msix_channels()
273 /* Fall back to single channel MSI */ in efx_probe_interrupts()
366 struct efx_channel *channel; in efx_set_interrupt_affinity() local
374 efx_for_each_channel(channel, efx) { in efx_set_interrupt_affinity()
378 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); in efx_set_interrupt_affinity()
384 struct efx_channel *channel; in efx_clear_interrupt_affinity() local
386 efx_for_each_channel(channel, efx) in efx_clear_interrupt_affinity()
387 irq_set_affinity_hint(channel->irq, NULL); in efx_clear_interrupt_affinity()
403 struct efx_channel *channel; in efx_remove_interrupts() local
406 efx_for_each_channel(channel, efx) in efx_remove_interrupts()
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| /linux/drivers/net/ethernet/sfc/siena/ |
| H A D | efx_channels.c | 157 * We need a channel per event queue, plus a VI per tx queue. in efx_allocate_msix_channels()
274 /* Fall back to single channel MSI */ in efx_siena_probe_interrupts()
367 struct efx_channel *channel; in efx_siena_set_interrupt_affinity() local
375 efx_for_each_channel(channel, efx) { in efx_siena_set_interrupt_affinity()
379 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); in efx_siena_set_interrupt_affinity()
385 struct efx_channel *channel; in efx_siena_clear_interrupt_affinity() local
387 efx_for_each_channel(channel, efx) in efx_siena_clear_interrupt_affinity()
388 irq_set_affinity_hint(channel->irq, NULL); in efx_siena_clear_interrupt_affinity()
404 struct efx_channel *channel; in efx_siena_remove_interrupts() local
407 efx_for_each_channel(channel, efx) in efx_siena_remove_interrupts()
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| /linux/drivers/rpmsg/ |
| H A D | qcom_smd.c | 30 * Each channel consists of a control item (channel info) and a ring buffer
31 * pair. The channel info carry information related to channel state, flow
37 * Upon creating a new channel the remote processor allocates channel info and
39 * interrupt is sent to the other end of the channel and a scan for new
40 * channels should be done. A channel never goes away, it will only change
44 * channel by setting the state of its end of the channel to "opening" and
46 * consume the channel. Upon finding a consumer we finish the handshake and the
47 * channel is up.
49 * Upon closing a channel, the remote processor will update the state of its
50 * end of the channel and signal us, we will then unregister any attached
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| H A D | qcom_glink_trace.h | 64 TP_PROTO(const char *remote, const char *channel, u16 lcid, u16 rcid, bool tx),
65 TP_ARGS(remote, channel, lcid, rcid, tx),
68 __string(channel, channel)
75 __assign_str(channel);
80 TP_printk("%s remote: %s channel: %s[%u/%u]",
83 __get_str(channel),
92 TP_PROTO(const char *remote, const char *channel, u16 lcid, u16 rcid, bool tx),
93 TP_ARGS(remote, channel, lcid, rcid, tx),
96 __string(channel, channel)
103 __assign_str(channel);
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| /linux/drivers/char/xillybus/ |
| H A D | xillybus_core.c | 102 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", in malformed_message()
120 struct xilly_channel *channel; in xillybus_isr() local
177 channel = ep->channels[msg_channel]; in xillybus_isr()
179 if (msg_dir) { /* Write channel */ in xillybus_isr()
180 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
184 spin_lock(&channel->wr_spinlock); in xillybus_isr()
185 channel->wr_buffers[msg_bufno]->end_offset = in xillybus_isr()
187 channel->wr_fpga_buf_idx = msg_bufno; in xillybus_isr()
188 channel->wr_empty = 0; in xillybus_isr()
189 channel->wr_sleepy = 0; in xillybus_isr()
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| /linux/drivers/staging/greybus/ |
| H A D | light.c | 65 static void gb_lights_channel_free(struct gb_channel *channel);
67 static struct gb_connection *get_conn_from_channel(struct gb_channel *channel) in get_conn_from_channel() argument
69 return channel->light->glights->connection; in get_conn_from_channel()
77 static bool is_channel_flash(struct gb_channel *channel) in is_channel_flash() argument
79 return !!(channel->mode & (GB_CHANNEL_MODE_FLASH | GB_CHANNEL_MODE_TORCH in is_channel_flash()
90 static struct led_classdev *get_channel_cdev(struct gb_channel *channel) in get_channel_cdev() argument
92 return &channel->fled.led_cdev; in get_channel_cdev()
98 struct gb_channel *channel; in get_channel_from_mode() local
102 channel = &light->channels[i]; in get_channel_from_mode()
103 if (channel->mode == mode) in get_channel_from_mode()
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| /linux/drivers/ipack/devices/ |
| H A D | ipoctal.c | 48 struct ipoctal_channel channel[NR_CHANNELS]; member
57 return container_of(chan, struct ipoctal, channel[index]); in chan_to_ipoctal()
60 static void ipoctal_reset_channel(struct ipoctal_channel *channel) in ipoctal_reset_channel() argument
62 iowrite8(CR_DISABLE_RX | CR_DISABLE_TX, &channel->regs->w.cr); in ipoctal_reset_channel()
63 channel->rx_enable = 0; in ipoctal_reset_channel()
64 iowrite8(CR_CMD_RESET_RX, &channel->regs->w.cr); in ipoctal_reset_channel()
65 iowrite8(CR_CMD_RESET_TX, &channel->regs->w.cr); in ipoctal_reset_channel()
66 iowrite8(CR_CMD_RESET_ERR_STATUS, &channel->regs->w.cr); in ipoctal_reset_channel()
67 iowrite8(CR_CMD_RESET_MR, &channel->regs->w.cr); in ipoctal_reset_channel()
72 struct ipoctal_channel *channel; in ipoctal_port_activate() local
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| /linux/drivers/most/ |
| H A D | most_snd.c | 28 * struct channel - private structure to keep channel specific data
31 * @iface: interface for which the channel belongs to
32 * @cfg: channel configuration
35 * @id: channel index
44 struct channel { struct
152 * get_channel - get pointer to channel
154 * @channel_id: channel ID
156 * This traverses the channel list and returns the channel matching the
159 * Returns pointer to channel on success or NULL otherwise.
161 static struct channel *get_channel(struct most_interface *iface, in get_channel()
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| /linux/drivers/dma/sh/ |
| H A D | rz-dmac.c | 204 static void rz_dmac_ch_writel(struct rz_dmac_chan *channel, unsigned int val, in rz_dmac_ch_writel() argument
208 writel(val, channel->ch_base + offset); in rz_dmac_ch_writel()
210 writel(val, channel->ch_cmn_base + offset); in rz_dmac_ch_writel()
213 static u32 rz_dmac_ch_readl(struct rz_dmac_chan *channel, in rz_dmac_ch_readl() argument
217 return readl(channel->ch_base + offset); in rz_dmac_ch_readl()
219 return readl(channel->ch_cmn_base + offset); in rz_dmac_ch_readl()
227 static void rz_lmdesc_setup(struct rz_dmac_chan *channel, in rz_lmdesc_setup() argument
232 channel->lmdesc.base = lmdesc; in rz_lmdesc_setup()
233 channel->lmdesc.head = lmdesc; in rz_lmdesc_setup()
234 channel->lmdesc.tail = lmdesc; in rz_lmdesc_setup()
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| /linux/drivers/hsi/clients/ |
| H A D | hsi_char.c | 66 * struct hsc_channel - hsi_char internal channel data
67 * @ch: channel number
68 * @flags: Keeps state of the channel (open/close, reading, writing)
116 static void hsc_add_tail(struct hsc_channel *channel, struct hsi_msg *msg, in hsc_add_tail() argument
121 spin_lock_irqsave(&channel->lock, flags); in hsc_add_tail()
123 spin_unlock_irqrestore(&channel->lock, flags); in hsc_add_tail()
126 static struct hsi_msg *hsc_get_first_msg(struct hsc_channel *channel, in hsc_get_first_msg() argument
132 spin_lock_irqsave(&channel->lock, flags); in hsc_get_first_msg()
140 spin_unlock_irqrestore(&channel->lock, flags); in hsc_get_first_msg()
161 static void hsc_reset_list(struct hsc_channel *channel, struct list_head *l) in hsc_reset_list() argument
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| /linux/sound/xen/ |
| H A D | xen_snd_front_evtchnl.c | 23 struct xen_snd_front_evtchnl *channel = dev_id; in evtchnl_interrupt_req() local
24 struct xen_snd_front_info *front_info = channel->front_info; in evtchnl_interrupt_req()
28 if (unlikely(channel->state != EVTCHNL_STATE_CONNECTED)) in evtchnl_interrupt_req()
31 mutex_lock(&channel->ring_io_lock); in evtchnl_interrupt_req()
34 rp = channel->u.req.ring.sring->rsp_prod; in evtchnl_interrupt_req()
43 for (i = channel->u.req.ring.rsp_cons; i != rp; i++) { in evtchnl_interrupt_req()
44 resp = RING_GET_RESPONSE(&channel->u.req.ring, i); in evtchnl_interrupt_req()
45 if (resp->id != channel->evt_id) in evtchnl_interrupt_req()
53 channel->u.req.resp_status = resp->status; in evtchnl_interrupt_req()
54 complete(&channel->u.req.completion); in evtchnl_interrupt_req()
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| /linux/drivers/firmware/arm_scmi/transports/ |
| H A D | optee.c | 22 * PTA_SCMI_CMD_CAPABILITIES - Get channel capabilities
32 * [in] value[0].a: Channel handle
35 * already identified and bound to channel handle in both SCMI agent
45 * [in] value[0].a: Channel handle
57 * PTA_SCMI_CMD_GET_CHANNEL - Get channel handle
61 * [in] value[0].a: Channel identifier
62 * [out] value[0].a: Returned channel handle
71 * [in] value[0].a: Channel handle
103 * struct scmi_optee_channel - Description of an OP-TEE SCMI channel
105 * @channel_id: OP-TEE channel ID used for this transport
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| /linux/drivers/net/ipa/ |
| H A D | gsi.c | 52 * of data to or from the IPA. A channel is implemented as a ring buffer,
59 * one or more TREs to a channel, the writer (either the IPA or an EE) writes
63 * Each channel has a GSI "event ring" associated with it. An event ring
64 * is implemented very much like a channel ring, but is always directed from
65 * the IPA to an EE. The IPA notifies an EE (such as the AP) about channel
66 * events by adding an entry to the event ring associated with the channel.
69 * to the channel TRE whose completion the event represents.
71 * Each TRE in a channel ring has a set of flags. One flag indicates whether
73 * an interrupt) in the channel's event ring. Other flags allow transfer
76 * to signal completion of channel transfers.
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | cirrus,ep9301-dma-m2p.yaml | 30 - description: m2p0 channel registers
31 - description: m2p1 channel registers
32 - description: m2p2 channel registers
33 - description: m2p3 channel registers
34 - description: m2p4 channel registers
35 - description: m2p5 channel registers
36 - description: m2p6 channel registers
37 - description: m2p7 channel registers
38 - description: m2p8 channel registers
39 - description: m2p9 channel registers
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| /linux/drivers/scsi/qla2xxx/ |
| H A D | qla_devtbl.h | 8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
16 "QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x108 */
17 "QCP2340", "cPCI to 2Gb FC, Single Channel", /* 0x109 */
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| /linux/sound/soc/codecs/ |
| H A D | tas5086.c | 70 #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
537 SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume",
540 SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume",
543 SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume",
567 SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]),
568 SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]),
569 SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]),
570 SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]),
571 SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]),
572 SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]),
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| /linux/drivers/net/wwan/iosm/ |
| H A D | iosm_ipc_imem_ops.c | 15 /* Open a packet data online channel between the network layer and CP. */
79 /* Initialize wwan channel */
142 /* return true if channel is ready for use */
144 struct ipc_mem_channel *channel) in ipc_imem_is_channel_active() argument
162 if (channel->state != IMEM_CHANNEL_RESERVED) { in ipc_imem_is_channel_active()
164 "ch[%d]:invalid channel state %d,expected %d", in ipc_imem_is_channel_active()
165 channel->channel_id, channel->state, in ipc_imem_is_channel_active()
174 channel->channel_id, phase); in ipc_imem_is_channel_active()
177 /* Check the full availability of the channel. */ in ipc_imem_is_channel_active()
178 if (channel->state != IMEM_CHANNEL_ACTIVE) { in ipc_imem_is_channel_active()
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| /linux/drivers/hsi/controllers/ |
| H A D | omap_ssi_regs.h | 33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
72 #define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) argument
82 # define SSI_NOTEMPTY(channel) (1 << (channel)) argument
91 #define SSI_SSR_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
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| /linux/sound/soc/sprd/ |
| H A D | sprd-mcdt.c | 57 /* Channel water mark definition */
62 /* DMA channel select definition */
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
128 static void sprd_mcdt_dac_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel, in sprd_mcdt_dac_set_watermark() argument
131 u32 reg = MCDT_DAC0_WTMK + channel * 4; in sprd_mcdt_dac_set_watermark()
140 static void sprd_mcdt_adc_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel, in sprd_mcdt_adc_set_watermark() argument
143 u32 reg = MCDT_ADC0_WTMK + channel * 4; in sprd_mcdt_adc_set_watermark()
152 static void sprd_mcdt_dac_dma_enable(struct sprd_mcdt_dev *mcdt, u8 channel, in sprd_mcdt_dac_dma_enable() argument
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable()
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| /linux/drivers/mailbox/ |
| H A D | mailbox-sti.c | 30 #define STI_IRQ_SET_OFFSET 0x24 /* Generate a Tx channel interrupt */
33 #define STI_ENA_SET_OFFSET 0x84 /* Enable a channel */
34 #define STI_ENA_CLR_OFFSET 0xa4 /* Disable a channel */
42 * @mbox: Representation of a communication channel controller
51 * A channel an be used for TX or RX
66 * @num_chan: Maximum number of channel per instance
74 * struct sti_channel - STi Mailbox allocated channel information
77 * @instance: Instance number channel resides in
78 * @channel: Channel number pertaining to this container
83 unsigned int channel; member
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| /linux/Documentation/sound/designs/ |
| H A D | channel-mapping-api.rst | 2 ALSA PCM channel-mapping API
10 The channel mapping API allows user to query the possible channel maps
11 and the current channel map, also optionally to modify the channel map
14 A channel map is an array of position for each PCM channel.
15 Typically, a stereo PCM stream has a channel map of
17 while a 4.0 surround PCM stream has a channel map of
20 The problem, so far, was that we had no standard channel map
21 explicitly, and applications had no way to know which channel
29 was no way to specify this because of lack of channel map
30 specification. These are the main motivations for the new channel
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| /linux/drivers/gpu/host1x/ |
| H A D | channel.c | 3 * Tegra host1x Channel
11 #include "channel.h"
43 struct host1x *host = dev_get_drvdata(job->channel->dev->parent); in host1x_job_submit()
49 struct host1x_channel *host1x_channel_get(struct host1x_channel *channel) in host1x_channel_get() argument
51 kref_get(&channel->refcount); in host1x_channel_get()
53 return channel; in host1x_channel_get()
58 * host1x_channel_get_index() - Attempt to get channel reference by index
60 * @index: Index of channel
62 * If channel number @index is currently allocated, increase its refcount
76 void host1x_channel_stop(struct host1x_channel *channel) in host1x_channel_stop() argument
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| /linux/Documentation/networking/ |
| H A D | ppp_generic.rst | 4 PPP Generic Driver and Channel Interface
26 the services of PPP ``channels``. A PPP channel encapsulates a
28 PPP channel implementation can be arbitrarily complex internally but
31 handle ioctl requests. Currently there are PPP channel
36 natural and straightforward way, by allowing more than one channel to
42 PPP channel API
49 Each channel has to provide two functions to the generic PPP layer,
53 send. The channel has the option of rejecting the frame for
55 and the channel should call the ppp_output_wakeup() function at a
61 program to control aspects of the channel's behaviour. This
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| /linux/drivers/firmware/tegra/ |
| H A D | bpmp.c | 28 channel_to_ops(struct tegra_bpmp_channel *channel) in channel_to_ops() argument
30 struct tegra_bpmp *bpmp = channel->bpmp; in channel_to_ops()
72 tegra_bpmp_channel_get_thread_index(struct tegra_bpmp_channel *channel) in tegra_bpmp_channel_get_thread_index() argument
74 struct tegra_bpmp *bpmp = channel->bpmp; in tegra_bpmp_channel_get_thread_index()
80 index = channel - channel->bpmp->threaded_channels; in tegra_bpmp_channel_get_thread_index()
95 static bool tegra_bpmp_is_response_ready(struct tegra_bpmp_channel *channel) in tegra_bpmp_is_response_ready() argument
97 const struct tegra_bpmp_ops *ops = channel_to_ops(channel); in tegra_bpmp_is_response_ready()
99 return ops->is_response_ready(channel); in tegra_bpmp_is_response_ready()
102 static bool tegra_bpmp_is_request_ready(struct tegra_bpmp_channel *channel) in tegra_bpmp_is_request_ready() argument
104 const struct tegra_bpmp_ops *ops = channel_to_ops(channel); in tegra_bpmp_is_request_ready()
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| /linux/drivers/tty/serial/jsm/ |
| H A D | jsm_tty.c | 66 struct jsm_channel *channel = in jsm_tty_get_mctrl() local
69 jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "start\n"); in jsm_tty_get_mctrl()
71 result = jsm_get_mstat(channel); in jsm_tty_get_mctrl()
76 jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "finish\n"); in jsm_tty_get_mctrl()
88 struct jsm_channel *channel = in jsm_tty_set_mctrl() local
91 jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "start\n"); in jsm_tty_set_mctrl()
94 channel->ch_mostat |= UART_MCR_RTS; in jsm_tty_set_mctrl()
96 channel->ch_mostat &= ~UART_MCR_RTS; in jsm_tty_set_mctrl()
99 channel->ch_mostat |= UART_MCR_DTR; in jsm_tty_set_mctrl()
101 channel->ch_mostat &= ~UART_MCR_DTR; in jsm_tty_set_mctrl()
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