57 /* Channel water mark definition */
62 /* DMA channel select definition */
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
128 static void sprd_mcdt_dac_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_dac_set_watermark()  argument
131 	u32 reg = MCDT_DAC0_WTMK + channel * 4;  in sprd_mcdt_dac_set_watermark()
140 static void sprd_mcdt_adc_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_adc_set_watermark()  argument
143 	u32 reg = MCDT_ADC0_WTMK + channel * 4;  in sprd_mcdt_adc_set_watermark()
152 static void sprd_mcdt_dac_dma_enable(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_dac_dma_enable()  argument
155 	u32 shift = MCDT_DAC_DMA_SHIFT + channel;  in sprd_mcdt_dac_dma_enable()
163 static void sprd_mcdt_adc_dma_enable(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_adc_dma_enable()  argument
167 		sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(channel), BIT(channel));  in sprd_mcdt_adc_dma_enable()
169 		sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(channel));  in sprd_mcdt_adc_dma_enable()
172 static void sprd_mcdt_ap_int_enable(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_ap_int_enable()  argument
176 		sprd_mcdt_update(mcdt, MCDT_INT_MSK_CFG0, BIT(channel),  in sprd_mcdt_ap_int_enable()
177 				 BIT(channel));  in sprd_mcdt_ap_int_enable()
179 		sprd_mcdt_update(mcdt, MCDT_INT_MSK_CFG0, 0, BIT(channel));  in sprd_mcdt_ap_int_enable()
182 static void sprd_mcdt_dac_write_fifo(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_dac_write_fifo()  argument
185 	u32 reg = MCDT_CH0_TXD + channel * 4;  in sprd_mcdt_dac_write_fifo()
190 static void sprd_mcdt_adc_read_fifo(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_adc_read_fifo()  argument
193 	u32 reg = MCDT_CH0_RXD + channel * 4;  in sprd_mcdt_adc_read_fifo()
198 static void sprd_mcdt_dac_dma_chn_select(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_dac_dma_chn_select()  argument
204 				 channel << MCDT_DMA_CH0_SEL_SHIFT,  in sprd_mcdt_dac_dma_chn_select()
210 				 channel << MCDT_DMA_CH1_SEL_SHIFT,  in sprd_mcdt_dac_dma_chn_select()
216 				 channel << MCDT_DMA_CH2_SEL_SHIFT,  in sprd_mcdt_dac_dma_chn_select()
222 				 channel << MCDT_DMA_CH3_SEL_SHIFT,  in sprd_mcdt_dac_dma_chn_select()
228 				 channel << MCDT_DMA_CH4_SEL_SHIFT,  in sprd_mcdt_dac_dma_chn_select()
234 static void sprd_mcdt_adc_dma_chn_select(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_adc_dma_chn_select()  argument
240 				 channel << MCDT_DMA_CH0_SEL_SHIFT,  in sprd_mcdt_adc_dma_chn_select()
246 				 channel << MCDT_DMA_CH1_SEL_SHIFT,  in sprd_mcdt_adc_dma_chn_select()
252 				 channel << MCDT_DMA_CH2_SEL_SHIFT,  in sprd_mcdt_adc_dma_chn_select()
258 				 channel << MCDT_DMA_CH3_SEL_SHIFT,  in sprd_mcdt_adc_dma_chn_select()
264 				 channel << MCDT_DMA_CH4_SEL_SHIFT,  in sprd_mcdt_adc_dma_chn_select()
270 static u32 sprd_mcdt_dma_ack_shift(u8 channel)  in sprd_mcdt_dma_ack_shift()  argument
272 	switch (channel) {  in sprd_mcdt_dma_ack_shift()
295 static void sprd_mcdt_dac_dma_ack_select(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_dac_dma_ack_select()  argument
298 	u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan;  in sprd_mcdt_dac_dma_ack_select()
300 	switch (channel) {  in sprd_mcdt_dac_dma_ack_select()
317 static void sprd_mcdt_adc_dma_ack_select(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_adc_dma_ack_select()  argument
320 	u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan;  in sprd_mcdt_adc_dma_ack_select()
322 	switch (channel) {  in sprd_mcdt_adc_dma_ack_select()
339 static bool sprd_mcdt_chan_fifo_sts(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_chan_fifo_sts()  argument
344 	switch (channel) {  in sprd_mcdt_chan_fifo_sts()
358 	switch (channel) {  in sprd_mcdt_chan_fifo_sts()
388 static void sprd_mcdt_dac_fifo_clear(struct sprd_mcdt_dev *mcdt, u8 channel)  in sprd_mcdt_dac_fifo_clear()  argument
390 	sprd_mcdt_update(mcdt, MCDT_FIFO_CLR, BIT(channel), BIT(channel));  in sprd_mcdt_dac_fifo_clear()
393 static void sprd_mcdt_adc_fifo_clear(struct sprd_mcdt_dev *mcdt, u8 channel)  in sprd_mcdt_adc_fifo_clear()  argument
395 	u32 shift = MCDT_ADC_FIFO_SHIFT + channel;  in sprd_mcdt_adc_fifo_clear()
400 static u32 sprd_mcdt_dac_fifo_avail(struct sprd_mcdt_dev *mcdt, u8 channel)  in sprd_mcdt_dac_fifo_avail()  argument
402 	u32 reg = MCDT_DAC0_FIFO_ADDR_ST + channel * 8;  in sprd_mcdt_dac_fifo_avail()
413 static u32 sprd_mcdt_adc_fifo_avail(struct sprd_mcdt_dev *mcdt, u8 channel)  in sprd_mcdt_adc_fifo_avail()  argument
415 	u32 reg = MCDT_ADC0_FIFO_ADDR_ST + channel * 8;  in sprd_mcdt_adc_fifo_avail()
426 static u32 sprd_mcdt_int_type_shift(u8 channel,  in sprd_mcdt_int_type_shift()  argument
429 	switch (channel) {  in sprd_mcdt_int_type_shift()
453 static void sprd_mcdt_chan_int_en(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_chan_int_en()  argument
456 	u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type);  in sprd_mcdt_chan_int_en()
458 	switch (channel) {  in sprd_mcdt_chan_int_en()
478 static void sprd_mcdt_chan_int_clear(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_chan_int_clear()  argument
481 	u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type);  in sprd_mcdt_chan_int_clear()
483 	switch (channel) {  in sprd_mcdt_chan_int_clear()
500 static bool sprd_mcdt_chan_int_sts(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_chan_int_sts()  argument
503 	u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type);  in sprd_mcdt_chan_int_sts()
505 	switch (channel) {  in sprd_mcdt_chan_int_sts()
556  * sprd_mcdt_chan_write - write data to the MCDT channel's fifo
557  * @chan: the MCDT channel
561  * Note: We can not write data to the channel fifo when enabling the DMA mode,
562  * otherwise the channel fifo data will be invalid.
564  * If there are not enough space of the channel fifo, it will return errors
586 		dev_err(mcdt->dev, "Channel fifo is full now\n");  in sprd_mcdt_chan_write()
608  * sprd_mcdt_chan_read - read data from the MCDT channel's fifo
609  * @chan: the MCDT channel
613  * Note: We can not read data from the channel fifo when enabling the DMA mode,
636 		dev_err(mcdt->dev, "Channel fifo is empty\n");  in sprd_mcdt_chan_read()
654  * sprd_mcdt_chan_int_enable - enable the interrupt mode for the MCDT channel
655  * @chan: the MCDT channel
659  * Now it only can enable fifo almost full interrupt for ADC channel and fifo
660  * almost empty interrupt for DAC channel. Morevoer for interrupt mode, user
664  * For ADC channel, user can start to read data once receiving one fifo full
665  * interrupt. For DAC channel, user can start to write data once receiving one
706 		dev_err(mcdt->dev, "Unsupported channel type\n");  in sprd_mcdt_chan_int_enable()
722  * sprd_mcdt_chan_int_disable - disable the interrupt mode for the MCDT channel
723  * @chan: the MCDT channel
762  * sprd_mcdt_chan_dma_enable - enable the DMA mode for the MCDT channel
763  * @chan: the MCDT channel
764  * @dma_chan: specify which DMA channel will be used for this MCDT channel
767  * Enable the DMA mode for the MCDT channel, that means we can use DMA to
768  * transfer data to the channel fifo and do not need reading/writing data
810 		dev_err(mcdt->dev, "Unsupported channel type\n");  in sprd_mcdt_chan_dma_enable()
824  * sprd_mcdt_chan_dma_disable - disable the DMA mode for the MCDT channel
825  * @chan: the MCDT channel
860  * sprd_mcdt_request_chan - request one MCDT channel
861  * @channel: channel id
862  * @type: channel type, it can be one ADC channel or DAC channel
864  * Rreturn NULL if no available channel.
866 struct sprd_mcdt_chan *sprd_mcdt_request_chan(u8 channel,  in sprd_mcdt_request_chan()  argument
874 		if (temp->type == type && temp->id == channel) {  in sprd_mcdt_request_chan()
890  * sprd_mcdt_free_chan - free one MCDT channel
891  * @chan: the channel to be freed
1005 MODULE_DESCRIPTION("Spreadtrum Multi-Channel Data Transfer Driver");