Lines Matching full:channel
102 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", in malformed_message()
120 struct xilly_channel *channel; in xillybus_isr() local
177 channel = ep->channels[msg_channel]; in xillybus_isr()
179 if (msg_dir) { /* Write channel */ in xillybus_isr()
180 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
184 spin_lock(&channel->wr_spinlock); in xillybus_isr()
185 channel->wr_buffers[msg_bufno]->end_offset = in xillybus_isr()
187 channel->wr_fpga_buf_idx = msg_bufno; in xillybus_isr()
188 channel->wr_empty = 0; in xillybus_isr()
189 channel->wr_sleepy = 0; in xillybus_isr()
190 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
192 wake_up_interruptible(&channel->wr_wait); in xillybus_isr()
195 /* Read channel */ in xillybus_isr()
197 if (msg_bufno >= channel->num_rd_buffers) { in xillybus_isr()
202 spin_lock(&channel->rd_spinlock); in xillybus_isr()
203 channel->rd_fpga_buf_idx = msg_bufno; in xillybus_isr()
204 channel->rd_full = 0; in xillybus_isr()
205 spin_unlock(&channel->rd_spinlock); in xillybus_isr()
207 wake_up_interruptible(&channel->rd_wait); in xillybus_isr()
208 if (!channel->rd_synchronous) in xillybus_isr()
211 &channel->rd_workitem, in xillybus_isr()
224 channel = ep->channels[msg_channel]; in xillybus_isr()
226 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
230 spin_lock(&channel->wr_spinlock); in xillybus_isr()
231 if (msg_bufno == channel->wr_host_buf_idx) in xillybus_isr()
232 channel->wr_ready = 1; in xillybus_isr()
233 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
235 wake_up_interruptible(&channel->wr_ready_wait); in xillybus_isr()
250 channel = ep->channels[msg_channel]; in xillybus_isr()
251 spin_lock(&channel->wr_spinlock); in xillybus_isr()
252 channel->wr_eof = msg_bufno; in xillybus_isr()
253 channel->wr_sleepy = 0; in xillybus_isr()
255 channel->wr_hangup = channel->wr_empty && in xillybus_isr()
256 (channel->wr_host_buf_idx == msg_bufno); in xillybus_isr()
258 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
260 wake_up_interruptible(&channel->wr_wait); in xillybus_isr()
433 struct xilly_channel *channel; in xilly_setupchannels() local
456 channel = devm_kcalloc(dev, ep->num_channels, in xilly_setupchannels()
458 if (!channel) in xilly_setupchannels()
467 ep->channels[0] = NULL; /* Channel 0 is message buf. */ in xilly_setupchannels()
472 channel->wr_buffers = NULL; in xilly_setupchannels()
473 channel->rd_buffers = NULL; in xilly_setupchannels()
474 channel->num_wr_buffers = 0; in xilly_setupchannels()
475 channel->num_rd_buffers = 0; in xilly_setupchannels()
476 channel->wr_fpga_buf_idx = -1; in xilly_setupchannels()
477 channel->wr_host_buf_idx = 0; in xilly_setupchannels()
478 channel->wr_host_buf_pos = 0; in xilly_setupchannels()
479 channel->wr_empty = 1; in xilly_setupchannels()
480 channel->wr_ready = 0; in xilly_setupchannels()
481 channel->wr_sleepy = 1; in xilly_setupchannels()
482 channel->rd_fpga_buf_idx = 0; in xilly_setupchannels()
483 channel->rd_host_buf_idx = 0; in xilly_setupchannels()
484 channel->rd_host_buf_pos = 0; in xilly_setupchannels()
485 channel->rd_full = 0; in xilly_setupchannels()
486 channel->wr_ref_count = 0; in xilly_setupchannels()
487 channel->rd_ref_count = 0; in xilly_setupchannels()
489 spin_lock_init(&channel->wr_spinlock); in xilly_setupchannels()
490 spin_lock_init(&channel->rd_spinlock); in xilly_setupchannels()
491 mutex_init(&channel->wr_mutex); in xilly_setupchannels()
492 mutex_init(&channel->rd_mutex); in xilly_setupchannels()
493 init_waitqueue_head(&channel->rd_wait); in xilly_setupchannels()
494 init_waitqueue_head(&channel->wr_wait); in xilly_setupchannels()
495 init_waitqueue_head(&channel->wr_ready_wait); in xilly_setupchannels()
497 INIT_DELAYED_WORK(&channel->rd_workitem, xillybus_autoflush); in xilly_setupchannels()
499 channel->endpoint = ep; in xilly_setupchannels()
500 channel->chan_num = i; in xilly_setupchannels()
502 channel->log2_element_size = 0; in xilly_setupchannels()
504 ep->channels[i] = channel++; in xilly_setupchannels()
524 "IDT requests channel out of range. Aborting.\n"); in xilly_setupchannels()
528 channel = ep->channels[channelnum]; /* NULL for msg channel */ in xilly_setupchannels()
531 channel->log2_element_size = ((format > 2) ? in xilly_setupchannels()
535 (1 << channel->log2_element_size); in xilly_setupchannels()
547 channel->num_rd_buffers = bufnum; in xilly_setupchannels()
548 channel->rd_buf_size = bytebufsize; in xilly_setupchannels()
549 channel->rd_allow_partial = allowpartial; in xilly_setupchannels()
550 channel->rd_synchronous = synchronous; in xilly_setupchannels()
551 channel->rd_exclusive_open = exclusive_open; in xilly_setupchannels()
552 channel->seekable = seekable; in xilly_setupchannels()
554 channel->rd_buffers = buffers; in xilly_setupchannels()
558 channel->num_wr_buffers = bufnum; in xilly_setupchannels()
559 channel->wr_buf_size = bytebufsize; in xilly_setupchannels()
561 channel->seekable = seekable; in xilly_setupchannels()
562 channel->wr_supports_nonempty = supports_nonempty; in xilly_setupchannels()
564 channel->wr_allow_partial = allowpartial; in xilly_setupchannels()
565 channel->wr_synchronous = synchronous; in xilly_setupchannels()
566 channel->wr_exclusive_open = exclusive_open; in xilly_setupchannels()
568 channel->wr_buffers = buffers; in xilly_setupchannels()
634 struct xilly_channel *channel; in xilly_obtain_idt() local
638 channel = endpoint->channels[1]; /* This should be generated ad-hoc */ in xilly_obtain_idt()
640 channel->wr_sleepy = 1; in xilly_obtain_idt()
643 (3 << 24), /* Opcode 3 for channel 0 = Send IDT */ in xilly_obtain_idt()
646 t = wait_event_interruptible_timeout(channel->wr_wait, in xilly_obtain_idt()
647 (!channel->wr_sleepy), in xilly_obtain_idt()
659 dma_sync_single_for_cpu(channel->endpoint->dev, in xilly_obtain_idt()
660 channel->wr_buffers[0]->dma_addr, in xilly_obtain_idt()
661 channel->wr_buf_size, in xilly_obtain_idt()
664 if (channel->wr_buffers[0]->end_offset != endpoint->idtlen) { in xilly_obtain_idt()
667 channel->wr_buffers[0]->end_offset, endpoint->idtlen); in xilly_obtain_idt()
671 if (crc32_le(~0, channel->wr_buffers[0]->addr, in xilly_obtain_idt()
677 version = channel->wr_buffers[0]->addr; in xilly_obtain_idt()
698 struct xilly_channel *channel = filp->private_data; in xillybus_read() local
706 if (channel->endpoint->fatal_error) in xillybus_read()
711 rc = mutex_lock_interruptible(&channel->wr_mutex); in xillybus_read()
718 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_read()
720 empty = channel->wr_empty; in xillybus_read()
721 ready = !empty || channel->wr_ready; in xillybus_read()
724 bufidx = channel->wr_host_buf_idx; in xillybus_read()
725 bufpos = channel->wr_host_buf_pos; in xillybus_read()
726 howmany = ((channel->wr_buffers[bufidx]->end_offset in xillybus_read()
727 + 1) << channel->log2_element_size) in xillybus_read()
735 channel->wr_host_buf_pos += howmany; in xillybus_read()
739 channel->wr_host_buf_pos = 0; in xillybus_read()
741 if (bufidx == channel->wr_fpga_buf_idx) { in xillybus_read()
742 channel->wr_empty = 1; in xillybus_read()
743 channel->wr_sleepy = 1; in xillybus_read()
744 channel->wr_ready = 0; in xillybus_read()
747 if (bufidx >= (channel->num_wr_buffers - 1)) in xillybus_read()
748 channel->wr_host_buf_idx = 0; in xillybus_read()
750 channel->wr_host_buf_idx++; in xillybus_read()
762 reached_eof = channel->wr_empty && in xillybus_read()
763 (channel->wr_host_buf_idx == channel->wr_eof); in xillybus_read()
764 channel->wr_hangup = reached_eof; in xillybus_read()
765 exhausted = channel->wr_empty; in xillybus_read()
766 waiting_bufidx = channel->wr_host_buf_idx; in xillybus_read()
768 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_read()
773 dma_sync_single_for_cpu(channel->endpoint->dev, in xillybus_read()
774 channel->wr_buffers[bufidx]->dma_addr, in xillybus_read()
775 channel->wr_buf_size, in xillybus_read()
780 channel->wr_buffers[bufidx]->addr in xillybus_read()
788 dma_sync_single_for_device(channel->endpoint->dev, in xillybus_read()
789 channel->wr_buffers[bufidx]->dma_addr, in xillybus_read()
790 channel->wr_buf_size, in xillybus_read()
797 * and the certain channel is protected with in xillybus_read()
798 * the channel-specific mutex. in xillybus_read()
801 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
803 channel->endpoint->registers + in xillybus_read()
808 mutex_unlock(&channel->wr_mutex); in xillybus_read()
822 (channel->wr_synchronous && channel->wr_allow_partial))) in xillybus_read()
852 channel->log2_element_size; in xillybus_read()
853 int buf_elements = channel->wr_buf_size >> in xillybus_read()
854 channel->log2_element_size; in xillybus_read()
861 if (channel->wr_synchronous) { in xillybus_read()
863 if (channel->wr_allow_partial && in xillybus_read()
868 if (!channel->wr_allow_partial && in xillybus_read()
870 (buf_elements * channel->num_wr_buffers))) in xillybus_read()
872 channel->num_wr_buffers - 1; in xillybus_read()
883 if (channel->wr_synchronous || in xillybus_read()
885 mutex_lock(&channel->endpoint->register_mutex); in xillybus_read()
888 channel->endpoint->registers + in xillybus_read()
891 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
894 channel->endpoint->registers + in xillybus_read()
897 mutex_unlock(&channel->endpoint-> in xillybus_read()
908 if (!channel->wr_allow_partial || in xillybus_read()
917 mutex_unlock(&channel->wr_mutex); in xillybus_read()
920 channel->wr_wait, in xillybus_read()
921 (!channel->wr_sleepy))) in xillybus_read()
925 &channel->wr_mutex)) in xillybus_read()
927 } while (channel->wr_sleepy); in xillybus_read()
932 if (channel->endpoint->fatal_error) in xillybus_read()
952 channel->wr_wait, in xillybus_read()
953 (!channel->wr_sleepy), in xillybus_read()
960 mutex_unlock(&channel->wr_mutex); in xillybus_read()
961 if (channel->endpoint->fatal_error) in xillybus_read()
980 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
983 channel->endpoint->registers + in xillybus_read()
996 mutex_unlock(&channel->wr_mutex); in xillybus_read()
998 if (channel->endpoint->fatal_error) in xillybus_read()
1014 static int xillybus_myflush(struct xilly_channel *channel, long timeout) in xillybus_myflush() argument
1025 if (channel->endpoint->fatal_error) in xillybus_myflush()
1027 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_myflush()
1032 * Don't flush a closed channel. This can happen when the work queued in xillybus_myflush()
1037 if (!channel->rd_ref_count) in xillybus_myflush()
1040 bufidx = channel->rd_host_buf_idx; in xillybus_myflush()
1043 channel->num_rd_buffers - 1 : in xillybus_myflush()
1046 end_offset_plus1 = channel->rd_host_buf_pos >> in xillybus_myflush()
1047 channel->log2_element_size; in xillybus_myflush()
1049 new_rd_host_buf_pos = channel->rd_host_buf_pos - in xillybus_myflush()
1050 (end_offset_plus1 << channel->log2_element_size); in xillybus_myflush()
1054 unsigned char *tail = channel->rd_buffers[bufidx]->addr + in xillybus_myflush()
1055 (end_offset_plus1 << channel->log2_element_size); in xillybus_myflush()
1059 channel->rd_leftovers[i] = *tail++; in xillybus_myflush()
1061 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_myflush()
1066 (channel->rd_full || in xillybus_myflush()
1067 (bufidx_minus1 != channel->rd_fpga_buf_idx))) { in xillybus_myflush()
1068 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1078 channel->rd_leftovers[3] = (new_rd_host_buf_pos != 0); in xillybus_myflush()
1082 if (bufidx == channel->rd_fpga_buf_idx) in xillybus_myflush()
1083 channel->rd_full = 1; in xillybus_myflush()
1084 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1086 if (bufidx >= (channel->num_rd_buffers - 1)) in xillybus_myflush()
1087 channel->rd_host_buf_idx = 0; in xillybus_myflush()
1089 channel->rd_host_buf_idx++; in xillybus_myflush()
1091 dma_sync_single_for_device(channel->endpoint->dev, in xillybus_myflush()
1092 channel->rd_buffers[bufidx]->dma_addr, in xillybus_myflush()
1093 channel->rd_buf_size, in xillybus_myflush()
1096 mutex_lock(&channel->endpoint->register_mutex); in xillybus_myflush()
1099 channel->endpoint->registers + fpga_buf_offset_reg); in xillybus_myflush()
1101 iowrite32((channel->chan_num << 1) | /* Channel ID */ in xillybus_myflush()
1104 channel->endpoint->registers + fpga_buf_ctrl_reg); in xillybus_myflush()
1106 mutex_unlock(&channel->endpoint->register_mutex); in xillybus_myflush()
1108 bufidx = channel->num_rd_buffers - 1; in xillybus_myflush()
1113 channel->rd_host_buf_pos = new_rd_host_buf_pos; in xillybus_myflush()
1121 * channel->rd_host_buf_idx the one after it. in xillybus_myflush()
1123 * If bufidx == channel->rd_fpga_buf_idx we're either empty or full. in xillybus_myflush()
1127 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_myflush()
1129 if (bufidx != channel->rd_fpga_buf_idx) in xillybus_myflush()
1130 channel->rd_full = 1; /* in xillybus_myflush()
1135 empty = !channel->rd_full; in xillybus_myflush()
1137 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1148 wait_event_interruptible(channel->rd_wait, in xillybus_myflush()
1149 (!channel->rd_full)); in xillybus_myflush()
1152 channel->rd_wait, in xillybus_myflush()
1153 (!channel->rd_full), in xillybus_myflush()
1155 dev_warn(channel->endpoint->dev, in xillybus_myflush()
1162 if (channel->rd_full) { in xillybus_myflush()
1169 mutex_unlock(&channel->rd_mutex); in xillybus_myflush()
1171 if (channel->endpoint->fatal_error) in xillybus_myflush()
1188 struct xilly_channel *channel = container_of( in xillybus_autoflush() local
1192 rc = xillybus_myflush(channel, -1); in xillybus_autoflush()
1194 dev_warn(channel->endpoint->dev, in xillybus_autoflush()
1197 dev_err(channel->endpoint->dev, in xillybus_autoflush()
1207 struct xilly_channel *channel = filp->private_data; in xillybus_write() local
1215 if (channel->endpoint->fatal_error) in xillybus_write()
1218 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_write()
1225 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_write()
1227 full = channel->rd_full; in xillybus_write()
1230 bufidx = channel->rd_host_buf_idx; in xillybus_write()
1231 bufpos = channel->rd_host_buf_pos; in xillybus_write()
1232 howmany = channel->rd_buf_size - bufpos; in xillybus_write()
1242 ((bufpos >> channel->log2_element_size) == 0))) { in xillybus_write()
1246 channel->rd_host_buf_pos += howmany; in xillybus_write()
1252 channel->rd_buf_size >> in xillybus_write()
1253 channel->log2_element_size; in xillybus_write()
1254 channel->rd_host_buf_pos = 0; in xillybus_write()
1262 channel->log2_element_size; in xillybus_write()
1264 channel->rd_host_buf_pos -= in xillybus_write()
1266 channel->log2_element_size; in xillybus_write()
1268 tail = channel-> in xillybus_write()
1271 channel->log2_element_size); in xillybus_write()
1274 i < channel->rd_host_buf_pos; in xillybus_write()
1276 channel->rd_leftovers[i] = in xillybus_write()
1280 if (bufidx == channel->rd_fpga_buf_idx) in xillybus_write()
1281 channel->rd_full = 1; in xillybus_write()
1283 if (bufidx >= (channel->num_rd_buffers - 1)) in xillybus_write()
1284 channel->rd_host_buf_idx = 0; in xillybus_write()
1286 channel->rd_host_buf_idx++; in xillybus_write()
1298 exhausted = channel->rd_full; in xillybus_write()
1300 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_write()
1304 channel->rd_buffers[bufidx]->addr; in xillybus_write()
1308 (channel->rd_leftovers[3] != 0)) { in xillybus_write()
1309 dma_sync_single_for_cpu(channel->endpoint->dev, in xillybus_write()
1310 channel->rd_buffers[bufidx]->dma_addr, in xillybus_write()
1311 channel->rd_buf_size, in xillybus_write()
1316 *head++ = channel->rd_leftovers[i]; in xillybus_write()
1318 channel->rd_leftovers[3] = 0; /* Clear flag */ in xillybus_write()
1322 channel->rd_buffers[bufidx]->addr + bufpos, in xillybus_write()
1330 dma_sync_single_for_device(channel->endpoint->dev, in xillybus_write()
1331 channel->rd_buffers[bufidx]->dma_addr, in xillybus_write()
1332 channel->rd_buf_size, in xillybus_write()
1335 mutex_lock(&channel->endpoint->register_mutex); in xillybus_write()
1338 channel->endpoint->registers + in xillybus_write()
1341 iowrite32((channel->chan_num << 1) | in xillybus_write()
1344 channel->endpoint->registers + in xillybus_write()
1347 mutex_unlock(&channel->endpoint-> in xillybus_write()
1350 channel->rd_leftovers[3] = in xillybus_write()
1351 (channel->rd_host_buf_pos != 0); in xillybus_write()
1355 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1357 if (channel->endpoint->fatal_error) in xillybus_write()
1360 if (!channel->rd_synchronous) in xillybus_write()
1363 &channel->rd_workitem, in xillybus_write()
1376 if ((bytes_done > 0) && channel->rd_allow_partial) in xillybus_write()
1390 if (wait_event_interruptible(channel->rd_wait, in xillybus_write()
1391 (!channel->rd_full))) { in xillybus_write()
1392 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1394 if (channel->endpoint->fatal_error) in xillybus_write()
1403 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1405 if (!channel->rd_synchronous) in xillybus_write()
1407 &channel->rd_workitem, in xillybus_write()
1410 if (channel->endpoint->fatal_error) in xillybus_write()
1416 if ((channel->rd_synchronous) && (bytes_done > 0)) { in xillybus_write()
1431 struct xilly_channel *channel; in xillybus_open() local
1441 channel = endpoint->channels[1 + index]; in xillybus_open()
1442 filp->private_data = channel; in xillybus_open()
1450 if ((filp->f_mode & FMODE_READ) && (!channel->num_wr_buffers)) in xillybus_open()
1453 if ((filp->f_mode & FMODE_WRITE) && (!channel->num_rd_buffers)) in xillybus_open()
1457 (channel->wr_synchronous || !channel->wr_allow_partial || in xillybus_open()
1458 !channel->wr_supports_nonempty)) { in xillybus_open()
1465 (channel->rd_synchronous || !channel->rd_allow_partial)) { in xillybus_open()
1479 rc = mutex_lock_interruptible(&channel->wr_mutex); in xillybus_open()
1485 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_open()
1491 (channel->wr_ref_count != 0) && in xillybus_open()
1492 (channel->wr_exclusive_open)) { in xillybus_open()
1498 (channel->rd_ref_count != 0) && in xillybus_open()
1499 (channel->rd_exclusive_open)) { in xillybus_open()
1505 if (channel->wr_ref_count == 0) { /* First open of file */ in xillybus_open()
1507 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_open()
1508 channel->wr_host_buf_idx = 0; in xillybus_open()
1509 channel->wr_host_buf_pos = 0; in xillybus_open()
1510 channel->wr_fpga_buf_idx = -1; in xillybus_open()
1511 channel->wr_empty = 1; in xillybus_open()
1512 channel->wr_ready = 0; in xillybus_open()
1513 channel->wr_sleepy = 1; in xillybus_open()
1514 channel->wr_eof = -1; in xillybus_open()
1515 channel->wr_hangup = 0; in xillybus_open()
1517 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_open()
1519 iowrite32(1 | (channel->chan_num << 1) | in xillybus_open()
1520 (4 << 24) | /* Opcode 4, open channel */ in xillybus_open()
1521 ((channel->wr_synchronous & 1) << 23), in xillybus_open()
1522 channel->endpoint->registers + in xillybus_open()
1526 channel->wr_ref_count++; in xillybus_open()
1530 if (channel->rd_ref_count == 0) { /* First open of file */ in xillybus_open()
1532 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_open()
1533 channel->rd_host_buf_idx = 0; in xillybus_open()
1534 channel->rd_host_buf_pos = 0; in xillybus_open()
1535 channel->rd_leftovers[3] = 0; /* No leftovers. */ in xillybus_open()
1536 channel->rd_fpga_buf_idx = channel->num_rd_buffers - 1; in xillybus_open()
1537 channel->rd_full = 0; in xillybus_open()
1539 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_open()
1541 iowrite32((channel->chan_num << 1) | in xillybus_open()
1542 (4 << 24), /* Opcode 4, open channel */ in xillybus_open()
1543 channel->endpoint->registers + in xillybus_open()
1547 channel->rd_ref_count++; in xillybus_open()
1552 mutex_unlock(&channel->rd_mutex); in xillybus_open()
1555 mutex_unlock(&channel->wr_mutex); in xillybus_open()
1557 if (!rc && (!channel->seekable)) in xillybus_open()
1566 struct xilly_channel *channel = filp->private_data; in xillybus_release() local
1571 if (channel->endpoint->fatal_error) in xillybus_release()
1575 mutex_lock(&channel->rd_mutex); in xillybus_release()
1577 channel->rd_ref_count--; in xillybus_release()
1579 if (channel->rd_ref_count == 0) { in xillybus_release()
1585 iowrite32((channel->chan_num << 1) | /* Channel ID */ in xillybus_release()
1586 (5 << 24), /* Opcode 5, close channel */ in xillybus_release()
1587 channel->endpoint->registers + in xillybus_release()
1590 mutex_unlock(&channel->rd_mutex); in xillybus_release()
1594 mutex_lock(&channel->wr_mutex); in xillybus_release()
1596 channel->wr_ref_count--; in xillybus_release()
1598 if (channel->wr_ref_count == 0) { in xillybus_release()
1599 iowrite32(1 | (channel->chan_num << 1) | in xillybus_release()
1600 (5 << 24), /* Opcode 5, close channel */ in xillybus_release()
1601 channel->endpoint->registers + in xillybus_release()
1607 * the channel or because of a user's EOF), but verify in xillybus_release()
1615 spin_lock_irqsave(&channel->wr_spinlock, in xillybus_release()
1617 buf_idx = channel->wr_fpga_buf_idx; in xillybus_release()
1618 eof = channel->wr_eof; in xillybus_release()
1619 channel->wr_sleepy = 1; in xillybus_release()
1620 spin_unlock_irqrestore(&channel->wr_spinlock, in xillybus_release()
1630 if (buf_idx == channel->num_wr_buffers) in xillybus_release()
1645 channel->wr_wait, in xillybus_release()
1646 (!channel->wr_sleepy))) in xillybus_release()
1649 if (channel->wr_sleepy) { in xillybus_release()
1650 mutex_unlock(&channel->wr_mutex); in xillybus_release()
1651 dev_warn(channel->endpoint->dev, in xillybus_release()
1658 mutex_unlock(&channel->wr_mutex); in xillybus_release()
1666 struct xilly_channel *channel = filp->private_data; in xillybus_llseek() local
1677 if (channel->endpoint->fatal_error) in xillybus_llseek()
1680 mutex_lock(&channel->wr_mutex); in xillybus_llseek()
1681 mutex_lock(&channel->rd_mutex); in xillybus_llseek()
1699 if (pos & ((1 << channel->log2_element_size) - 1)) { in xillybus_llseek()
1704 mutex_lock(&channel->endpoint->register_mutex); in xillybus_llseek()
1706 iowrite32(pos >> channel->log2_element_size, in xillybus_llseek()
1707 channel->endpoint->registers + fpga_buf_offset_reg); in xillybus_llseek()
1709 iowrite32((channel->chan_num << 1) | in xillybus_llseek()
1711 channel->endpoint->registers + fpga_buf_ctrl_reg); in xillybus_llseek()
1713 mutex_unlock(&channel->endpoint->register_mutex); in xillybus_llseek()
1716 mutex_unlock(&channel->rd_mutex); in xillybus_llseek()
1717 mutex_unlock(&channel->wr_mutex); in xillybus_llseek()
1725 * Since seekable devices are allowed only when the channel is in xillybus_llseek()
1733 channel->rd_leftovers[3] = 0; in xillybus_llseek()
1740 struct xilly_channel *channel = filp->private_data; in xillybus_poll() local
1744 poll_wait(filp, &channel->endpoint->ep_wait, wait); in xillybus_poll()
1754 if (!channel->wr_synchronous && channel->wr_supports_nonempty) { in xillybus_poll()
1755 poll_wait(filp, &channel->wr_wait, wait); in xillybus_poll()
1756 poll_wait(filp, &channel->wr_ready_wait, wait); in xillybus_poll()
1758 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_poll()
1759 if (!channel->wr_empty || channel->wr_ready) in xillybus_poll()
1762 if (channel->wr_hangup) in xillybus_poll()
1769 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_poll()
1773 * If partial data write is disallowed on a write() channel, in xillybus_poll()
1778 if (channel->rd_allow_partial) { in xillybus_poll()
1779 poll_wait(filp, &channel->rd_wait, wait); in xillybus_poll()
1781 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_poll()
1782 if (!channel->rd_full) in xillybus_poll()
1784 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_poll()
1787 if (channel->endpoint->fatal_error) in xillybus_poll()