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/freebsd/sys/riscv/vmm/
H A Dvmm_riscv.c164 struct hypcsr *csrs; in vmmops_vcpu_restore_csrs() local
166 csrs = &hypctx->guest_csrs; in vmmops_vcpu_restore_csrs()
168 csr_write(vsstatus, csrs->vsstatus); in vmmops_vcpu_restore_csrs()
169 csr_write(vsie, csrs->vsie); in vmmops_vcpu_restore_csrs()
170 csr_write(vstvec, csrs->vstvec); in vmmops_vcpu_restore_csrs()
171 csr_write(vsscratch, csrs->vsscratch); in vmmops_vcpu_restore_csrs()
172 csr_write(vsepc, csrs->vsepc); in vmmops_vcpu_restore_csrs()
173 csr_write(vscause, csrs->vscause); in vmmops_vcpu_restore_csrs()
174 csr_write(vstval, csrs->vstval); in vmmops_vcpu_restore_csrs()
175 csr_write(hvip, csrs->hvip); in vmmops_vcpu_restore_csrs()
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/freebsd/sys/contrib/device-tree/Bindings/net/pcs/
H A Dsnps,dw-xpcs.yaml21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
49 of the MDIO bus device. If DW XPCS CSRs space is accessed over the
57 so the corresponding subset would be mapped to the lowest 255 CSRs.
65 The way the CSRs are mapped to the memory is platform depended. Since
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,cpu-intc.txt4 RISC-V cores include Control Status Registers (CSRs) which are local to each
6 Some of these CSRs are used to control local interrupts connected to the core.
40 definition of the hart whose CSRs control these local interrupts.
H A Driscv,cpu-intc.yaml10 RISC-V cores include Control Status Registers (CSRs) which are local to
12 software. Some of these CSRs are used to control local interrupts connected
H A Driscv,imsics.yaml19 a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dsnps,dw-pcie-ep.yaml47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
73 set of viewport CSRs mapped into the PL space. Note iATU is
79 CSRs mapped in a non-standard base address. The registers offset
86 PCS and PHY CSRs accessible over a dedicated memory mapped
H A Dsnps,dw-pcie.yaml56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
82 set of viewport CSRs mapped into the PL space. Note iATU is
88 CSRs mapped in a non-standard base address. The registers offset
95 PCS and PHY CSRs accessible over a dedicated memory mapped
/freebsd/sys/dev/qat_c2xxx/
H A Dqat_c2xxxreg.h90 * 32K AE CSRs and transfer registers, 8K CHAP/PMU,
91 * 4K EP CSRs, 4K MSI-X Tables
96 /* PETRINGCSR: 8K 16 bundles of ET Ring CSRs */
/freebsd/share/man/man4/
H A Diavf.4144 4 Queue Pairs (QP) and associated Configuration Status Registers (CSRs)
151 1 control queue, with iavf descriptors, CSRs and ring format
153 5 MSI\-X interrupt vectors and corresponding iavf CSRs
/freebsd/lib/msun/riscv/
H A Dfenv.h108 __asm __volatile("csrs fflags, %0" :: "r"(__fcsr & __excepts)); in fesetexceptflag()
117 __asm __volatile("csrs fflags, %0" :: "r"(__excepts)); in feraiseexcept()
/freebsd/sys/contrib/device-tree/Bindings/soc/litex/
H A Dlitex,soc-controller.yaml13 operations and provide functions for other drivers to read/write CSRs
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DShrinkWrap.cpp357 // Check if this regmask clobbers any of the CSRs. in INITIALIZE_PASS_DEPENDENCY()
399 /// or def of CSRs/FI to MBB.
425 /// Collect blocks reachable by use or def of CSRs/FI.
629 // Find blocks reachable from the use or def of CSRs/FI. in postShrinkWrapping()
750 // use/def CSRs in updateSaveRestorePoints()
752 // All the uses/defs of CSRs are dominated by Save and post-dominated in updateSaveRestorePoints()
753 // by Restore. However, the CSRs uses are still reachable after in updateSaveRestorePoints()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSystemOperands.td75 // User Floating-Point CSRs
341 // User Vector CSRs
383 // Machine-level CSRs
404 // Supervisor-level CSRs
420 // Hypervisor and VS CSRs
452 // Resumable Non-Maskable Interrupts(Smrnmi) CSRs
/freebsd/sys/riscv/riscv/
H A Dswtch.S48 csrs sstatus, t0
97 csrs sstatus, t0
161 csrs sstatus, t0
/freebsd/sys/riscv/include/
H A Dasm.h66 csrs sstatus, tmp
H A Dcpufunc.h69 "csrs sstatus, %0" in intr_restore()
/freebsd/sys/dev/bhnd/bhndb/
H A Dbhndb_pci_sprom.c34 * Provides support for early PCI bridge cores that vend SPROM CSRs
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dsnps,dw-umctl2-ddrc.yaml60 A standard set of the clock sources contains CSRs bus clock, AXI-ports
/freebsd/contrib/llvm-project/lldb/source/Utility/
H A DRISCV_DWARF_Registers.h120 // The vector extension adds seven unprivileged CSRs
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td339 // the order of CSRs in CSR_iOS.
343 // CSRs that are handled by prologue, epilogue.
346 // CSRs that are handled explicitly via copies.
/freebsd/sys/cddl/dev/dtrace/riscv/
H A Ddtrace_asm.S67 csrs sstatus, a0
/freebsd/sys/dev/qat/qat_common/
H A Dadf_gen4_hw_data.c235 * mmio write to 32bit CSRs. in adf_gen4_set_ssm_wdtimer()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h92 /// Stack probing calls preserve different CSRs to the normal CC.
H A DAArch64FrameLowering.h136 /// Returns true if CSRs should be paired.
/freebsd/sys/dev/qat/include/common/
H A Dicp_qat_hal.h140 #define ICP_QAT_EP_OFFSET_4XXX 0x200000 /* HI MMIO CSRs */

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