riscv: T-HEAD early locore workaround

The T-HEAD custom PTE bits are defined in such a way that the
default/normal memory type is non-zero value. This _unthoughtful_ choice
means that, unlike the Sv

riscv: T-HEAD early locore workaround

The T-HEAD custom PTE bits are defined in such a way that the
default/normal memory type is non-zero value. This _unthoughtful_ choice
means that, unlike the Svpbmt and non-Svpbmt cases, this field cannot be
left bare in our bootstrap PTEs, or the hardware will fail to proceed
far enough in boot (cache strangeness). On the other hand, we cannot
unconditionally apply the PTE_THEAD_MA_NONE attributes, as this is not
compatible with spec-compliant RISC-V hardware, and will result in a
fatal exception.

Therefore, in order to handle this errata, we are forced to perform a
check of the CPU type at the first moment possible. Do so, and fix up
the PTEs with the correct memory attribute bits in the T-HEAD case.

Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D47458

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sys: Remove $FreeBSD$: two-line .h pattern

Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/

Add .cfi_{start,end}proc for RISC-V assembly functions

This allows GDB to print more useful backtraces when setting a breakpoint
on an assembly function.

Reviewed By: jhb
Differential Revision: htt

Add .cfi_{start,end}proc for RISC-V assembly functions

This allows GDB to print more useful backtraces when setting a breakpoint
on an assembly function.

Reviewed By: jhb
Differential Revision: https://reviews.freebsd.org/D27177

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MFHead @349234

Sponsored by: The FreeBSD Foundation

Fix global pointer relaxations in the RISC-V kernel

The gp register is intended to used by the linker as another means of
performing relaxations, and should point to the small data section (.sdata).

Fix global pointer relaxations in the RISC-V kernel

The gp register is intended to used by the linker as another means of
performing relaxations, and should point to the small data section (.sdata).

Currently gp is being used as the pcpu pointer within the kernel, but the more
appropriate choice for this is the tp register, which is unused.

Swap existing usage of gp with tp within the kernel, and set up gp properly
at boot with the value of __global_pointer$ for all harts.

Additionally, remove some cases of accessing tp from the PCB, as it is not
part of the per-thread state. The user's tp and gp should be tracked only
through the trapframe.

Reviewed by: markj, jhb
Approved by: markj (mentor)
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D19893

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Merge ^/head r338392 through r338594.

Permit supervisor to access user VA space for certain functions only.

This is done by setting SUM (permit Supervisor User Memory access)
bit in sstatus register.

The functions we allow access for a

Permit supervisor to access user VA space for certain functions only.

This is done by setting SUM (permit Supervisor User Memory access)
bit in sstatus register.

The functions we allow access for are routines in assembly that
explicitly handle crossing the user kernel boundary.

Approved by: re (kib)
Sponsored by: DARPA, AFRL

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Merge ^/head r308227 through r308490.

o Add support for long double.
o Add support for latest RISC-V GNU toolchain.

Sponsored by: DARPA, AFRL
Sponsored by: HEIF5

MFH

Sponsored by: The FreeBSD Foundation

Merge ^/head r294961 through r295350.

Access pcpup using gp register.

MFH r289384-r293170

Sponsored by: The FreeBSD Foundation

MFH @r292599

This includes the pluggable TCP framework and other chnages to the
netstack to track for VNET stability.

Security: The FreeBSD Foundation

Import RISC-V machine headers. This is a minimal set required to compile
kernel and userland.

Reviewed by: andrew, imp, kib
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Differential Revision: https

Import RISC-V machine headers. This is a minimal set required to compile
kernel and userland.

Reviewed by: andrew, imp, kib
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Differential Revision: https://reviews.freebsd.org/D4554

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