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/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.c178 adf_enable_error_interrupts(struct resource *csr) in adf_enable_error_interrupts() argument
180 ADF_CSR_WR(csr, ADF_ERRMSK0, ADF_200XX_ERRMSK0_CERR); /* ME0-ME3 */ in adf_enable_error_interrupts()
181 ADF_CSR_WR(csr, ADF_ERRMSK1, ADF_200XX_ERRMSK1_CERR); /* ME4-ME5 */ in adf_enable_error_interrupts()
182 ADF_CSR_WR(csr, ADF_ERRMSK5, ADF_200XX_ERRMSK5_CERR); /* SSM2 */ in adf_enable_error_interrupts()
185 adf_csr_fetch_and_and(csr, ADF_ERRMSK3, ADF_200XX_VF2PF1_16); in adf_enable_error_interrupts()
188 ADF_CSR_WR(csr, ADF_200XX_RICPPINTCTL, ADF_200XX_RICPP_EN); in adf_enable_error_interrupts()
191 ADF_CSR_WR(csr, ADF_200XX_TICPPINTCTL, ADF_200XX_TICPP_EN); in adf_enable_error_interrupts()
194 ADF_CSR_WR(csr, ADF_200XX_CPP_CFC_ERR_CTRL, ADF_200XX_CPP_CFC_UE); in adf_enable_error_interrupts()
201 struct resource *csr = misc_bar->virt_addr; in adf_disable_error_interrupts() local
204 ADF_CSR_WR(csr, in adf_disable_error_interrupts()
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/freebsd/sys/powerpc/booke/
H A Dmachdep_e500.c56 uint32_t csr; in booke_enable_l1_cache() local
59 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
60 if ((csr & L1CSR0_DCE) == 0) { in booke_enable_l1_cache()
65 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
66 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0) in booke_enable_l1_cache()
68 (csr & L1CSR0_DCE) ? "en" : "dis"); in booke_enable_l1_cache()
71 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
72 if ((csr & L1CSR1_ICE) == 0) { in booke_enable_l1_cache()
77 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
78 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0) in booke_enable_l1_cache()
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/freebsd/sys/dev/qat/qat_api/firmware/include/
H A Dicp_qat_hw_20_comp.h28 * Definition of the hw config csr. This representation has to be further
59 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_comp_20_config_csr_lower_t csr) in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER() argument
64 csr.algo, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
69 csr.sd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
75 csr.edmm, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
80 csr.hbs, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
85 csr.mmctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
90 csr.hash_col, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
95 csr.hash_update, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
100 csr.skip_ctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
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/freebsd/sys/dev/qat/include/common/
H A Dicp_qat_hal.h144 #define CAP_CSR_ADDR(csr) (csr + handle->hal_cap_g_ctl_csr_addr_v) argument
145 #define SET_CAP_CSR(handle, csr, val) \ argument
146 ADF_CSR_WR(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr), val)
147 #define GET_CAP_CSR(handle, csr) \ argument
148 ADF_CSR_RD(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr))
149 #define SET_GLB_CSR(handle, csr, val) \ argument
153 SET_CAP_CSR((handle), (csr), (val)) : \
154 SET_CAP_CSR((handle), (csr) + GLOBAL_CSR, val); \
156 #define GET_GLB_CSR(handle, csr) \ argument
160 GET_CAP_CSR((handle), (csr)) : \
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H A Dadf_accel_devices.h463 /* helper enum for performing CSR operations */
469 /* 32-bit CSR write macro */
473 /* 64-bit CSR write macro */
488 /* 32-bit CSR read macro */
491 /* 64-bit CSR read macro */
532 adf_csr_fetch_and_and(struct resource *csr, size_t offs, unsigned long mask) in adf_csr_fetch_and_and() argument
534 unsigned int val = ADF_CSR_RD(csr, offs); in adf_csr_fetch_and_and()
537 ADF_CSR_WR(csr, offs, val); in adf_csr_fetch_and_and()
541 adf_csr_fetch_and_or(struct resource *csr, size_t offs, unsigned long mask) in adf_csr_fetch_and_or() argument
543 unsigned int val = ADF_CSR_RD(csr, offs); in adf_csr_fetch_and_or()
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/freebsd/sys/dev/qat/qat_common/
H A Dadf_hw_arbiter.c53 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb() local
63 WRITE_CSR_ARB_SARCONFIG(csr, info.arbiter_offset, arb, arb_cfg); in adf_init_arb()
73 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_gen2_arb() local
88 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, in adf_init_gen2_arb()
162 struct resource *csr = csr_addr; in adf_disable_ring_arb() local
169 arbenable = csr_ops->read_csr_ring_srv_arb_en(csr, bank_nr); in adf_disable_ring_arb()
171 csr_ops->write_csr_ring_srv_arb_en(csr, bank_nr, arbenable); in adf_disable_ring_arb()
181 struct resource *csr; in adf_exit_arb() local
187 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb()
193 WRITE_CSR_ARB_SARCONFIG(csr, info.arbiter_offset, i, 0); in adf_exit_arb()
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H A Dadf_dev_err.c178 struct resource *csr = misc_bar->virt_addr; in adf_print_err_registers() local
184 val = ADF_CSR_RD(csr, adf_err_regs[i].offs); in adf_print_err_registers()
196 val = adf_accel_err_regs[i].read(csr, accel); in adf_print_err_registers()
224 struct resource *csr, in adf_handle_slice_hang() argument
227 u32 slice_hang = ADF_CSR_RD(csr, slice_hang_offset); in adf_handle_slice_hang()
264 ADF_CSR_WR(csr, slice_hang_offset, slice_hang); in adf_handle_slice_hang()
280 struct resource *csr = misc_bar->virt_addr; in adf_check_slice_hang() local
281 u32 errsou3 = ADF_CSR_RD(csr, ADF_ERRSOU3); in adf_check_slice_hang()
282 u32 errsou5 = ADF_CSR_RD(csr, ADF_ERRSOU5); in adf_check_slice_hang()
306 if (ADF_CSR_RD(csr, ADF_INTSTATSSM(accel_num)) & in adf_check_slice_hang()
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H A Dqat_hal.c112 unsigned int csr, in qat_hal_rd_ae_csr() argument
118 *value = GET_AE_CSR(handle, ae, csr); in qat_hal_rd_ae_csr()
123 pr_err("QAT: Read CSR timeout\n"); in qat_hal_rd_ae_csr()
130 unsigned int csr, in qat_hal_wr_ae_csr() argument
136 SET_AE_CSR(handle, ae, csr, value); in qat_hal_wr_ae_csr()
141 pr_err("QAT: Write CSR Timeout\n"); in qat_hal_wr_ae_csr()
166 unsigned int csr = (1 << ACS_ABO_BITPOS); in qat_hal_wait_cycles() local
174 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &csr); in qat_hal_wait_cycles()
184 if (elapsed_cycles >= 8 && !(csr & (1 << ACS_ABO_BITPOS))) in qat_hal_wait_cycles()
208 unsigned int csr, new_csr; in qat_hal_set_ae_ctx_mode() local
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H A Dadf_freebsd_transport_debug.c23 struct resource *csr = ring->bank->csr_addr; in adf_ring_show() local
32 head = csr_ops->read_csr_ring_head(csr, in adf_ring_show()
35 tail = csr_ops->read_csr_ring_tail(csr, in adf_ring_show()
38 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
139 struct resource *csr = bank->csr_addr; in adf_bank_show() local
145 head = csr_ops->read_csr_ring_head(csr, in adf_bank_show()
148 tail = csr_ops->read_csr_ring_tail(csr, in adf_bank_show()
151 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_bank_show()
H A Dadf_gen4_hw_data.c154 reset_ring_pair(struct resource *csr, u32 bank_number) in reset_ring_pair() argument
166 ADF_CSR_WR(csr, in reset_ring_pair()
172 val = ADF_CSR_RD(csr, ADF_WQM_CSR_RPRESETSTS(bank_number)); in reset_ring_pair()
182 ADF_CSR_WR(csr, in reset_ring_pair()
193 struct resource *csr; in adf_gen4_ring_pair_reset() local
199 csr = (&GET_BARS(accel_dev)[etr_bar_id])->virt_addr; in adf_gen4_ring_pair_reset()
201 ret = reset_ring_pair(csr, bank_number); in adf_gen4_ring_pair_reset()
/freebsd/sys/riscv/include/
H A Driscvreg.h229 #define csr_swap(csr, val) \ argument
232 __asm __volatile("csrrwi %0, " #csr ", %1" \
235 __asm __volatile("csrrw %0, " #csr ", %1" \
240 #define csr_write(csr, val) \ argument
242 __asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \
244 __asm __volatile("csrw " #csr ", %0" :: "r" (val)); \
247 #define csr_set(csr, val) \ argument
249 __asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \
251 __asm __volatile("csrs " #csr ", %0" :: "r" (val)); \
254 #define csr_clear(csr, val) \ argument
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/freebsd/sys/dev/usb/controller/
H A Dmusb_otg.c403 uint8_t csr; in musbotg_dev_ctrl_setup_rx() local
421 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); in musbotg_dev_ctrl_setup_rx()
423 DPRINTFN(4, "csr=0x%02x\n", csr); in musbotg_dev_ctrl_setup_rx()
429 if (csr & MUSB2_MASK_CSR0L_DATAEND) { in musbotg_dev_ctrl_setup_rx()
437 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { in musbotg_dev_ctrl_setup_rx()
441 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); in musbotg_dev_ctrl_setup_rx()
445 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { in musbotg_dev_ctrl_setup_rx()
450 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); in musbotg_dev_ctrl_setup_rx()
458 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { in musbotg_dev_ctrl_setup_rx()
529 uint8_t csr, csrh; in musbotg_host_ctrl_setup_tx() local
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/freebsd/share/doc/smm/02.config/
H A Dc.t63 controller tm0 at uba? csr 0172520 vector tmintr
66 device dh0 at uba? csr 0160020 vector dhrint dhxint
67 device dm0 at uba? csr 0170500 vector dmintr
68 device dh1 at uba? csr 0160040 vector dhrint dhxint
69 device dh2 at uba? csr 0160060 vector dhrint dhxint
91 controller sc0 at uba? csr 0176700 vector upintr
94 controller hk0 at uba? csr 0177440 vector rkintr
100 device acc0 at uba? csr 0167600 vector accrint accxint
102 device ec0 at uba? csr 0164330 vector ecrint eccollide ecxint
103 device il0 at uba? csr 0164000 vector ilrint ilcint
H A D5.t122 controller tm0 at uba0 csr 0172520 vector tmintr
125 device dh0 at uba0 csr 0160020 vector dhrint dhxint
126 device dm0 at uba0 csr 0170500 vector dmintr
127 device dh1 at uba0 csr 0160040 vector dhrint dhxint
128 device dh2 at uba0 csr 0160060 vector dhrint dhxint
151 controller tm0 at uba? csr 0172520 vector tmintr
154 device dh0 at uba? csr 0160020 vector dhrint dhxint
155 device dm0 at uba? csr 0170500 vector dmintr
156 device dh1 at uba? csr 0160040 vector dhrint dhxint
157 device dh2 at uba? csr 0160060 vector dhrint dhxint
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxgene.txt36 - reg : shall be a list of address and length pairs describing the CSR
40 may include "csr-reg" and/or "div-reg". If this property
42 only "csr-reg".
49 - csr-offset : Offset to the CSR reset register from the reset address base.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
55 - divider-offset : Offset to the divider CSR register from the divider base.
96 reg-name = "csr-reg";
120 reg-names = "csr-reg", "div-reg";
121 csr-offset = <0x0>;
[all …]
H A Dnxp,imx95-blk-ctl.yaml16 - nxp,imx95-lvds-csr
17 - nxp,imx95-display-csr
18 - nxp,imx95-camera-csr
20 - nxp,imx95-vpu-csr
51 compatible = "nxp,imx95-vpu-csr", "syscon";
/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_res_part.c64 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_sym_threads() local
73 WRITE_CSR_WQM(csr, in adf_enable_sym_threads()
82 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_asym_threads() local
93 WRITE_CSR_WQM(csr, in adf_enable_asym_threads()
102 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_dc_threads() local
111 WRITE_CSR_WQM(csr, in adf_enable_dc_threads()
125 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb_c4xxx() local
136 WRITE_CSR_WQM(csr, in adf_init_arb_c4xxx()
170 struct resource *csr; in adf_exit_arb_c4xxx() local
176 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb_c4xxx()
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H A Dadf_c4xxx_hw_data.c209 struct resource *csr = misc_bar->virt_addr; in c4xxx_set_ssm_wdtimer() local
228 ADF_CSR_WR(csr, ADF_C4XXX_SSMWDTL_OFFSET(accel), ssm_wdt_low); in c4xxx_set_ssm_wdtimer()
229 ADF_CSR_WR(csr, ADF_C4XXX_SSMWDTH_OFFSET(accel), ssm_wdt_high); in c4xxx_set_ssm_wdtimer()
230 ADF_CSR_WR(csr, in c4xxx_set_ssm_wdtimer()
233 ADF_CSR_WR(csr, in c4xxx_set_ssm_wdtimer()
252 struct resource *csr = misc_bar->virt_addr; in c4xxx_check_slice_hang() local
259 u32 errsou10 = ADF_CSR_RD(csr, ADF_C4XXX_ERRSOU10); in c4xxx_check_slice_hang()
269 fw_irq_source = ADF_CSR_RD(csr, ADF_INTSTATSSM(accel_num)); in c4xxx_check_slice_hang()
271 ADF_CSR_RD(csr, ADF_C4XXX_IAINTSTATSSM(accel_num)); in c4xxx_check_slice_hang()
284 adf_csr_fetch_and_and(csr, slice_hang_offset, ~0); in c4xxx_check_slice_hang()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-storm.dtsi196 reg-names = "csr-reg", "div-reg";
197 csr-offset = <0x0>;
198 csr-mask = <0x2>;
225 reg-names = "csr-reg";
234 reg-names = "csr-reg";
235 csr-mask = <0xa>;
245 reg-names = "csr-reg";
246 csr-mask = <0x3>;
256 reg-names = "csr-reg";
257 csr-mask = <0x3>;
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/freebsd/crypto/openssl/test/certs/
H A Dmkcert.sh113 csr=$(req "$key" "CN = $cn") || return 1
114 echo "$csr" |
154 csr=$(req "$key" "CN = $cn") || return 1
155 echo "$csr" |
175 csr=$(req "$key" "CN = $cn") || return 1
176 echo "$csr" |
183 # Note: takes csr on stdin, so must be used with $0 req like this:
222 # Note: takes csr on stdin, so must be used with $0 req like this:
264 csr=$(req "$key" "CN = $cn") || return 1
265 echo "$csr" |
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dfsl,imx8qxp-csr.yaml4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
14 Registers(CSR) module represents a set of miscellaneous registers of a
19 should consider all subnodes of the CSR module as separate child devices.
28 - fsl,imx8qxp-mipi-lvds-csr
29 - fsl,imx8qm-lvds-csr
45 description: The possible child devices of the CSR module.
58 const: fsl,imx8qxp-mipi-lvds-csr
68 const: fsl,imx8qm-lvds-csr
81 compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp57 const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); in runOnMachineFunction() local
63 if (CSR[I] == 0) { in runOnMachineFunction()
71 if (CSR[I] != LastCalleeSavedRegs[I]) { in runOnMachineFunction()
81 // Build a CSRAlias map. Every CSR alias saves the last in runOnMachineFunction()
82 // overlapping CSR. in runOnMachineFunction()
84 for (const MCPhysReg *I = CSR; *I; ++I) { in runOnMachineFunction()
93 // Even if CSR list is same, we could have had a different allocation order in runOnMachineFunction()
96 for (const MCPhysReg *I = CSR; *I; ++I) in runOnMachineFunction()
123 /// registers filtered out. Volatile registers come first followed by CSR
124 /// aliases ordered according to the CSR order specified by the target.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gnss/
H A Dsirfstar.yaml16 by CSR (Cambridge Silicon Radio) and in 2012 the CSR GPS business was
17 acquired by Samsung, while some products remained with CSR. In 2014 CSR
29 - csr,gsd4t
30 - csr,csrg05ta03-icje-r
/freebsd/contrib/wpa/src/crypto/
H A Dcrypto_wolfssl.c3213 /* BEGIN Certificate Signing Request (CSR) APIs */
3223 /* For parsed csr should be read-only for higher levels */
3225 Cert c; /* For generating a csr */
3233 static void crypto_csr_init_type(struct crypto_csr *csr, enum cert_type type, in crypto_csr_init_type() argument
3238 if (csr->type == type) in crypto_csr_init_type()
3241 switch (csr->type) { in crypto_csr_init_type()
3243 wc_FreeDecodedCert(&csr->req.dc); in crypto_csr_init_type()
3247 wc_SetCert_Free(&csr->req.c); in crypto_csr_init_type()
3256 wc_InitDecodedCert(&csr->req.dc, source, in_sz, NULL); in crypto_csr_init_type()
3259 err = wc_InitCert(&csr->req.c); in crypto_csr_init_type()
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H A Dcrypto.h1196 * Internal data structure for CSR. The contents is specific to the used
1203 * enum crypto_csr_name - CSR name type
1214 * enum crypto_csr_attr - CSR attribute
1221 * crypto_csr_init - Initialize empty CSR
1222 * Returns: Pointer to CSR data or %NULL on failure
1227 * crypto_csr_verify - Initialize CSR from CertificationRequest
1230 * Returns: Pointer to CSR data or %NULL on failure or if signature is invalid
1235 * crypto_csr_deinit - Free CSR structure
1236 * @csr: CSR structure from @crypto_csr_init() or crypto_csr_verify()
1238 void crypto_csr_deinit(struct crypto_csr *csr);
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