| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-iio-sx9324 | 6 SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout 18 By default, during the first phase, [PH0], CS0 is measured, 21 [PH1], CS1 is measured, CS0 and CS2 are shield: 23 [PH2], CS2 is measured, CS0 and CS1 are shield:
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| H A D | sysfs-class-watchdog | 110 chip at CS0 after booting from the alternate 114 from (CS0->CS1, CS1->CS0) to (CS0->CS0, 119 the SoC is in normal mapping state (i.e. booted from CS0),
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| /linux/Documentation/devicetree/bindings/iio/proximity/ |
| H A D | semtech,sx9310.yaml | 46 semtech,cs0-ground: 47 description: Indicates the CS0 sensor is connected to ground. 56 0 1 - CS0 + CS1 58 0 1 2 3 - CS0 + CS1 + CS2 + CS3 124 semtech,cs0-ground;
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| /linux/drivers/memory/ |
| H A D | renesas-xspi-if-regs.h | 23 /* xSPI Command Map Configuration Register 0 CS0 */ 28 /* xSPI Command Map Configuration Register 1 CS0 */ 34 /* xSPI Command Map Configuration Register 2 CS0 */ 40 /* xSPI Link I/O Configuration Register CS0 */ 80 /* xSPI Command Calibration Control Register 0 CS0 */
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | marvell,armada-370-pinctrl.txt | 29 mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0), 45 mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0) 53 mpp32 32 gpio, spi0(cs0) 54 mpp33 33 gpio, dev(bootcs), spi0(cs0) 71 mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0), 86 mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
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| H A D | marvell,armada-38x-pinctrl.txt | 36 mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) 43 mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) 77 mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)
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| H A D | marvell,armada-39x-pinctrl.txt | 36 mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) 44 mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) 81 mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)
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| H A D | marvell,armada-375-pinctrl.txt | 24 mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) 46 mpp30 30 gpio, ge1(txd0), spi1(cs0)
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| H A D | marvell,armada-98dx3236-pinctrl.txt | 17 mpp3 3 gpio, spi0(cs0), dev(ad11) 18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
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| /linux/arch/hexagon/kernel/ |
| H A D | ptrace.c | 64 membuf_store(&to, regs->cs0); in genregs_get() 112 INEXT(®s->cs0, cs0); in genregs_set() 116 ignore_offset = offsetof(struct user_regs_struct, cs0); in genregs_set()
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| H A D | signal.c | 54 err |= __put_user(regs->cs0, &sc->sc_regs.cs0); in setup_sigcontext() 84 err |= __get_user(regs->cs0, &sc->sc_regs.cs0); in restore_sigcontext()
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| H A D | vm_events.c | 35 printk(KERN_EMERG "cs0: \t0x%08lx cs1: 0x%08lx\n", in show_regs() 36 regs->cs0, regs->cs1); in show_regs()
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| /linux/arch/hexagon/include/uapi/asm/ |
| H A D | user.h | 59 /* cs0 and cs1 are only available with HEXAGON_ARCH_VERSION >= 4 */ 60 unsigned long cs0; member
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| /linux/drivers/ata/ |
| H A D | pata_octeon_cf.c | 56 unsigned int cs0; member 167 octeon_cf_set_boot_reg_cfg(cf_port->cs0, div); in octeon_cf_set_piomode() 175 reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0)); in octeon_cf_set_piomode() 204 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64); in octeon_cf_set_piomode() 809 void __iomem *cs0; in octeon_cf_probe() local 838 cf_port->cs0 = upper_32_bits(reg); in octeon_cf_probe() 892 cs0 = devm_ioremap(&pdev->dev, res_cs0->start, in octeon_cf_probe() 894 if (!cs0) in octeon_cf_probe() 911 base = cs0 + 0x800; in octeon_cf_probe() 919 base = cs0; in octeon_cf_probe() [all …]
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| /linux/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-armada-370.c | 86 MPP_FUNCTION(0x4, "spi1", "cs0"), 149 MPP_FUNCTION(0x4, "spi1", "cs0")), 185 MPP_FUNCTION(0x1, "spi0", "cs0")), 189 MPP_FUNCTION(0x2, "spi0", "cs0")), 261 MPP_FUNCTION(0x4, "spi1", "cs0"), 317 MPP_FUNCTION(0x1, "dev", "cs0"),
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| H A D | pinctrl-armada-375.c | 78 MPP_FUNCTION(0x2, "spi0", "cs0"), 79 MPP_FUNCTION(0x3, "spi1", "cs0"), 148 MPP_FUNCTION(0x5, "spi0", "cs0"), 190 MPP_FUNCTION(0x3, "spi1", "cs0"), 326 MPP_FUNCTION(0x6, "dev", "cs0")),
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| /linux/Documentation/translations/zh_CN/scheduler/ |
| H A D | sched-capacity.rst | 266 cpusets cs0 cs1 272 mkdir /sys/fs/cgroup/cpuset/cs0 273 echo 0-1 > /sys/fs/cgroup/cpuset/cs0/cpuset.cpus 274 echo 0 > /sys/fs/cgroup/cpuset/cs0/cpuset.mems
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | marvell,orion-spi.yaml | 39 - description: CS0 MBUS target/attribute registers for direct mode 91 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
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| /linux/include/net/ |
| H A D | dscp.h | 22 * well-known DSCP values such as CS0-CS7, AFxx, EF, and VOICE-ADMIT. 45 /* CS0 is some times called default (DF) */
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| /linux/arch/arm/boot/dts/intel/ixp/ |
| H A D | intel-ixp42x-iomega-nas100d.dts | 93 /* The first 16MB region at CS0 on the expansion bus */ 99 * mapped in at CS0.
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| H A D | intel-ixp42x-dlink-dsm-g600.dts | 103 /* The first 16MB region at CS0 on the expansion bus */ 109 * mapped in at CS0.
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap3-gta04a5one.dts | 44 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ 55 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3568-pinctrl.dtsi | 2241 spi0m0_cs0: spi0m0-cs0 { 2266 spi0m1_cs0: spi0m1-cs0 { 2286 spi1m0_cs0: spi1m0-cs0 { 2311 spi1m1_cs0: spi1m1-cs0 { 2331 spi2m0_cs0: spi2m0-cs0 { 2356 spi2m1_cs0: spi2m1-cs0 { 2383 spi3m0_cs0: spi3m0-cs0 { 2408 spi3m1_cs0: spi3m1-cs0 { 2828 spi0m0_cs0_hs: spi0m0-cs0 { 2853 spi0m1_cs0_hs: spi0m1-cs0 { [all …]
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| /linux/arch/powerpc/platforms/85xx/ |
| H A D | p1022_ds.c | 239 /* Make sure CS0 and CS1 are programmed */ in p1022ds_set_monitor_port() 241 pr_err("p1022ds: CS0 and/or CS1 is not programmed\n"); in p1022ds_set_monitor_port() 265 pr_err("p1022ds: could not determine physical address for CS0" in p1022ds_set_monitor_port() 278 pr_err("p1022ds: could not ioremap CS0 address %llx\n", in p1022ds_set_monitor_port()
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| /linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-370-xp.dtsi | 60 devbus_cs0: devbus-cs0 { 269 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */ 287 <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
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