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Searched full:cpucp (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/mailbox/
H A Dqcom-cpucp-mbox.c33 * @tx_base: Base address of the CPUCP tx registers
34 * @rx_base: Base address of the CPUCP rx registers
50 struct qcom_cpucp_mbox *cpucp = data; in qcom_cpucp_mbox_irq_fn() local
54 status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); in qcom_cpucp_mbox_irq_fn()
57 u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); in qcom_cpucp_mbox_irq_fn()
58 struct mbox_chan *chan = &cpucp->chans[i]; in qcom_cpucp_mbox_irq_fn()
65 writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); in qcom_cpucp_mbox_irq_fn()
74 struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox); in qcom_cpucp_mbox_startup() local
78 val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); in qcom_cpucp_mbox_startup()
80 writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); in qcom_cpucp_mbox_startup()
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H A DKconfig325 tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
328 Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
329 controller driver enables communication between AP and CPUCP. Say
H A DMakefile72 obj-$(CONFIG_QCOM_CPUCP_MBOX) += qcom-cpucp-mbox.o
/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom,cpucp-mbox.yaml4 $id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
7 title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
13 The CPUSS Control Processor (CPUCP) mailbox controller enables communication
14 between AP and CPUCP by acting as a doorbell between them.
19 - const: qcom,x1e80100-cpucp-mbox
23 - description: CPUCP rx register region
24 - description: CPUCP tx register region
45 compatible = "qcom,x1e80100-cpucp-mbox";
/linux/include/linux/habanalabs/
H A Dcpucp_if.h419 * CpuCP Primary Queue Packets
422 * messages to CpuCP, usually either to SET some value into a H/W periphery or
428 * communication from the host's driver to CpuCP will *always* be in
442 * During device initialization phase, the host will pass to CpuCP that address.
451 * Upon receiving the interrupt (#121), CpuCP will read the message from the
452 * DDR. In case the message is a SET operation, CpuCP will first perform the
454 * message is a GET operation, CpuCP will first fill the results section on the
455 * device DDR and then write to the fence object. If an error occurred, CpuCP
464 * so the value being put by the host's driver matches the value read by CpuCP
529 * structure. The host's driver passes the max size it allows the CpuCP to
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H A Dhl_boot_if.h332 * HWMON enum mapping to cpucp enums.
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,osm-l3.yaml34 - qcom,sm6375-cpucp-l3
/linux/drivers/accel/habanalabs/common/
H A Dfirmware_if.c957 dev_err(hdev->dev, "CPUCP array data is too big\n"); in hl_fw_send_msi_info_msg()
985 dev_err(hdev->dev, "failed to send CPUCP array data\n"); in hl_fw_send_msi_info_msg()
1168 "Failed to handle CpuCP total energy pkt, error %d\n", rc); in hl_fw_cpucp_total_energy_get()
2476 "Using a single interrupt interface towards cpucp"); in hl_fw_dynamic_update_linux_interrupt_if()
3329 dev_err(hdev->dev, "failed to send CPUCP data of generic fw pkt\n"); in hl_fw_send_generic_request()
H A Dhabanalabs.h702 * @supports_advanced_cpucp_rc: true if new cpucp opcodes are supported.
/linux/arch/arm64/boot/dts/qcom/
H A Dsdx75.dtsi303 cpucp_fw_mem: cpucp-fw@87c00000 {
H A Dqdu1000.dtsi292 cpucp_fw_mem: cpucp-fw@80b00000 {
H A Dsm8750.dtsi318 cpucp_mem: cpucp@81200000 {
359 cpucp_scandump_mem: cpucp-scandump@82000000 {
H A Dx1e80100.dtsi474 cpucp_log_mem: cpucp-log@80e00000 {
479 cpucp_mem: cpucp@80e40000 {
8039 compatible = "qcom,x1e80100-cpucp-mbox";
H A Dsa8775p.dtsi781 cpucp_backup_mem: cpucp-backup@91b40000 {
927 cpucp_fw_mem: cpucp-fw@db200000 {
H A Dsar2130p.dtsi335 cpucp_fw_mem: cpucp-fw@80b00000 {
H A Dsm8550.dtsi654 cpucp_fw_mem: cpucp-fw-region@d8140000 {
H A Dsc7280.dtsi139 cpucp_mem: cpucp@80b00000 {
/linux/include/uapi/drm/
H A Dhabanalabs_accel.h890 * @cpucp_version: The CPUCP f/w version.
/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi.c843 * GIC-security-bit can ONLY be set by CPUCP, so in this stage in gaudi_early_init()
1616 dev_err(hdev->dev, "Failed to get cpucp info\n"); in gaudi_late_init()
/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c885 dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc); in goya_late_init()
/linux/
H A DMAINTAINERS20712 QUALCOMM CPUCP MAILBOX DRIVER
20716 F: Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
20717 F: drivers/mailbox/qcom-cpucp-mbox.c