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/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos8895-clock.yaml21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
23 derived from CMU_TOP.
73 - description: CMU_FSYS0 BUS clock (from CMU_TOP)
74 - description: CMU_FSYS0 DPGTC clock (from CMU_TOP)
75 - description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)
76 - description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)
77 - description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)
99 - description: CMU_FSYS1 BUS clock (from CMU_TOP)
100 - description: CMU_FSYS1 PCIE clock (from CMU_TOP)
101 - description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)
[all …]
H A Dsamsung,exynos7885-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
81 - description: CMU_CORE bus clock (from CMU_TOP)
82 - description: CCI clock (from CMU_TOP)
83 - description: G3D clock (from CMU_TOP)
103 - description: CMU_FSYS bus clock (from CMU_TOP)
104 - description: MMC_CARD clock (from CMU_TOP)
105 - description: MMC_EMBD clock (from CMU_TOP)
106 - description: MMC_SDIO clock (from CMU_TOP)
107 - description: USB30DRD clock (from CMU_TOP)
[all …]
H A Dsamsung,exynos990-clock.yaml21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
23 derived from CMU_TOP.
74 - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
75 - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
94 - description: CMU_HSI0 BUS clock (from CMU_TOP)
95 - description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
96 - description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
97 - description: CMU_HSI0 DPGTC clock (from CMU_TOP)
118 - description: CMU_PERIS BUS clock (from CMU_TOP)
153 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
[all …]
/linux/include/dt-bindings/clock/
H A Dsamsung,exynosautov9.h12 /* CMU_TOP */
19 /* MUX in CMU_TOP */
68 /* DIV in CMU_TOP */
120 /* GAT in CMU_TOP */
H A Dexynos7885.h11 /* CMU_TOP */
H A Dexynos5260-clk.h14 /* List Of Clocks For CMU_TOP */
H A Dsamsung,exynos990.h11 /* CMU_TOP */
H A Dsamsung,exynos8895.h12 /* CMU_TOP */
H A Dexynos5433.h10 /* CMU_TOP */
/linux/drivers/clk/samsung/
H A Dclk-exynos7885.c24 /* ---- CMU_TOP ------------------------------------------------------------- */
26 /* Register Offset definitions for CMU_TOP (0x12060000) */
164 /* List of parent clocks for Muxes in CMU_TOP */
168 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
176 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
187 /* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */
361 /* Register CMU_TOP early, as it's a dependency for other early domains */
H A Dclk-exynos850.c34 /* ---- CMU_TOP ------------------------------------------------------------- */
36 /* Register Offset definitions for CMU_TOP (0x120e0000) */
243 /* List of parent clocks for Muxes in CMU_TOP */
247 /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
249 /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
252 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
263 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
267 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
271 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
274 /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
[all …]
H A Dclk-cpu.c432 * doesn't affect CPU speed). So CPUCLx_SWITCH divider from CMU_TOP is used
445 /* Divider from CMU_TOP */ in exynos850_alt_parent_set_max_rate()
449 /* Divider's parent from CMU_TOP */ in exynos850_alt_parent_set_max_rate()
H A Dclk-exynos5250.c269 * CMU_TOP
360 * CMU_TOP
453 * CMU_TOP
611 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
H A Dclk-exynosautov9.c30 /* ---- CMU_TOP ------------------------------------------------------------ */
32 /* Register Offset definitions for CMU_TOP (0x1b240000) */
365 /* List of parent clocks for Muxes in CMU_TOP */
965 /* Register CMU_TOP early, as it's a dependency for other early domains */
H A Dclk-exynos5260.h364 *Registers for CMU_TOP
H A Dclk-exynosautov920.c34 /* ---- CMU_TOP ------------------------------------------------------------ */
36 /* Register Offset definitions for CMU_TOP (0x11000000) */
351 /* List of parent clocks for Muxes in CMU_TOP */
1011 /* Register CMU_TOP early, as it's a dependency for other early domains */
H A Dclk-exynos990.c25 /* ---- CMU_TOP ------------------------------------------------------------- */
27 /* Register Offset definitions for CMU_TOP (0x1a330000) */
469 /* Parent clock list for CMU_TOP muxes */
1180 /* Register CMU_TOP early, as it's a dependency for other early domains */
H A Dclk-exynos8895.c26 /* ---- CMU_TOP ------------------------------------------------------------- */
28 /* Register Offset definitions for CMU_TOP (0x15a80000) */
518 /* List of parent clocks for Muxes in CMU_TOP */
1308 /* Register CMU_TOP early, as it's a dependency for other early domains */
H A Dclk-exynos2200.c30 /* ---- CMU_TOP ------------------------------------------------------------ */
32 /* Register Offset definitions for CMU_TOP (0x1a320000) */
735 /* List of parent clocks for Muxes in CMU_TOP */
1935 /* Register CMU_TOP early, as it's a dependency for other early domains */
H A Dclk-gs101.c33 /* ---- CMU_TOP ------------------------------------------------------------- */
35 /* Register Offset definitions for CMU_TOP (0x1e080000) */
659 /* List of parent clocks for Muxes in CMU_TOP */
1450 /* Register CMU_TOP early, as it's a dependency for other early domains */
H A Dclk-exynos5433.c45 * Register offset definitions for CMU_TOP