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/linux/include/dt-bindings/clock/
H A Dexynos5410.h48 #define CLK_TSADC 270 macro
H A Ds5pv210.h154 #define CLK_TSADC 136 macro
H A Dexynos5420.h79 #define CLK_TSADC 270 macro
H A Dexynos4.h164 #define CLK_TSADC 326 macro
H A Dexynos3250.h199 #define CLK_TSADC 193 macro
H A Drockchip,rk3576-cru.h146 #define CLK_TSADC 128 macro
H A Drockchip,rk3588-cru.h173 #define CLK_TSADC 158 macro
H A Drk3568-cru.h337 #define CLK_TSADC 273 macro
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dsamsung,exynos-adc.yaml162 clocks = <&cmu CLK_TSADC>,
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410.dtsi252 clocks = <&clock CLK_TSADC>;
H A Ds5pv210.dtsi145 clocks = <&clocks CLK_TSADC>;
H A Dexynos4x12.dtsi322 clocks = <&clock CLK_TSADC>;
H A Dexynos3250.dtsi620 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
H A Dexynos5420.dtsi1205 clocks = <&clock CLK_TSADC>;
/linux/drivers/clk/samsung/
H A Dclk-exynos5410.c212 GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
H A Dclk-exynos4.c947 GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
974 GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
H A Dclk-s5pv210.c570 GATE(CLK_TSADC, "tsadc", "dout_pclkp", CLK_GATE_IP3, 24, 0, 0),
H A Dclk-exynos3250.c642 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
/linux/drivers/clk/rockchip/
H A Dclk-rk3568.c1189 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0,
H A Dclk-rk3576.c637 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
H A Dclk-rk3328.c456 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
H A Dclk-rk3308.c426 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
H A Dclk-px30.c764 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
H A Dclk-rk3588.c1215 COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0,
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-base.dtsi2661 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2663 assigned-clocks = <&cru CLK_TSADC>;

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