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Searched full:clk_top_msdc50_0_sel (Results 1 – 23 of 23) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt7629-clk.h94 #define CLK_TOP_MSDC50_0_SEL 84 macro
H A Dmt7622-clk.h79 #define CLK_TOP_MSDC50_0_SEL 67 macro
H A Dmediatek,mt6795-clk.h104 #define CLK_TOP_MSDC50_0_SEL 93 macro
H A Dmt8173-clk.h106 #define CLK_TOP_MSDC50_0_SEL 96 macro
H A Dmt6765-clk.h144 #define CLK_TOP_MSDC50_0_SEL 109 macro
H A Dmediatek,mt8365-clk.h83 #define CLK_TOP_MSDC50_0_SEL 73 macro
H A Dmt2712-clk.h143 #define CLK_TOP_MSDC50_0_SEL 112 macro
H A Dmt8192-clk.h36 #define CLK_TOP_MSDC50_0_SEL 24 macro
/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml333 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365-evk.dts166 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
H A Dmt8173-elm.dtsi394 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
H A Dmt8365.dtsi661 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
H A Dmt7622.dtsi704 <&topckgen CLK_TOP_MSDC50_0_SEL>;
H A Dmt6795.dtsi684 <&topckgen CLK_TOP_MSDC50_0_SEL>;
H A Dmt8192.dtsi1396 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
/linux/drivers/clk/mediatek/
H A Dclk-mt7622.c412 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
H A Dclk-mt6795-topckgen.c473 TOP_MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x70, 16, 4, 23, 0),
H A Dclk-mt8173-topckgen.c552 MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents,
H A Dclk-mt7629.c486 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
H A Dclk-mt8365.c440 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
H A Dclk-mt6765.c412 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
H A Dclk-mt2712.c663 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents,
H A Dclk-mt8192.c606 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",