Searched full:clk_top_eth_sel (Results 1 – 13 of 13) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 86 #define CLK_TOP_ETH_SEL 76 macro
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| H A D | mt8516-clk.h | 175 #define CLK_TOP_ETH_SEL 143 macro
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| H A D | mt7622-clk.h | 71 #define CLK_TOP_ETH_SEL 59 macro
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| H A D | mediatek,mt8365-clk.h | 109 #define CLK_TOP_ETH_SEL 99 macro
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| /linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt7629.dtsi | 443 clocks = <&topckgen CLK_TOP_ETH_SEL>,
466 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | mediatek,net.yaml | 430 clocks = <&topckgen CLK_TOP_ETH_SEL>,
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt7622.c | 392 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
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| H A D | clk-mt8516.c | 393 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
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| H A D | clk-mt7629.c | 468 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
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| H A D | clk-mt8167.c | 572 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
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| H A D | clk-mt8365.c | 514 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0,
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8365.dtsi | 700 clocks = <&topckgen CLK_TOP_ETH_SEL>,
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| H A D | mt7622.dtsi | 970 clocks = <&topckgen CLK_TOP_ETH_SEL>,
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