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/linux/drivers/clk/sunxi-ng/
H A DMakefile3 obj-$(CONFIG_SUNXI_CCU) += sunxi-ccu.o
6 sunxi-ccu-y += ccu_common.o
7 sunxi-ccu-y += ccu_mmc_timing.o
8 sunxi-ccu-y += ccu_reset.o
11 sunxi-ccu-y += ccu_div.o
12 sunxi-ccu-y += ccu_frac.o
13 sunxi-ccu-y += ccu_gate.o
14 sunxi-ccu-y += ccu_mux.o
15 sunxi-ccu-y += ccu_mult.o
16 sunxi-ccu-y += ccu_phase.o
[all …]
H A DKconfig11 tristate "Support for the Allwinner newer F1C100s CCU"
16 tristate "Support for the Allwinner D1/R528/T113 CCU"
21 tristate "Support for the Allwinner D1/R528/T113 PRCM CCU"
26 tristate "Support for the Allwinner A64 CCU"
31 tristate "Support for the Allwinner A100 CCU"
36 tristate "Support for the Allwinner A100 PRCM CCU"
41 tristate "Support for the Allwinner H6 CCU"
46 tristate "Support for the Allwinner H616 CCU"
51 tristate "Support for the Allwinner H6 and H616 PRCM CCU"
56 tristate "Support for the Allwinner A523/T527 CCU"
[all …]
H A Dccu_reset.c16 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev); in ccu_reset_assert() local
17 const struct ccu_reset_map *map = &ccu->reset_map[id]; in ccu_reset_assert()
21 spin_lock_irqsave(ccu->lock, flags); in ccu_reset_assert()
23 reg = readl(ccu->base + map->reg); in ccu_reset_assert()
24 writel(reg & ~map->bit, ccu->base + map->reg); in ccu_reset_assert()
26 spin_unlock_irqrestore(ccu->lock, flags); in ccu_reset_assert()
34 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev); in ccu_reset_deassert() local
35 const struct ccu_reset_map *map = &ccu->reset_map[id]; in ccu_reset_deassert()
39 spin_lock_irqsave(ccu->lock, flags); in ccu_reset_deassert()
41 reg = readl(ccu->base + map->reg); in ccu_reset_deassert()
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-ccu.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
22 - allwinner,sun4i-a10-ccu
23 - allwinner,sun5i-a10s-ccu
24 - allwinner,sun5i-a13-ccu
25 - allwinner,sun6i-a31-ccu
26 - allwinner,sun7i-a20-ccu
27 - allwinner,sun8i-a23-ccu
28 - allwinner,sun8i-a33-ccu
29 - allwinner,sun8i-a83t-ccu
30 - allwinner,sun8i-a83t-r-ccu
[all …]
H A Dbrcm,kona-ccu.yaml4 $id: http://devicetree.org/schemas/clock/brcm,kona-ccu.yaml#
7 title: Broadcom Kona family clock control units (CCU)
15 Broadcom "Kona" style clock control unit (CCU) is a clock provider that
25 - brcm,bcm11351-aon-ccu
26 - brcm,bcm11351-hub-ccu
27 - brcm,bcm11351-master-ccu
28 - brcm,bcm11351-root-ccu
29 - brcm,bcm11351-slave-ccu
30 - brcm,bcm21664-aon-ccu
31 - brcm,bcm21664-master-ccu
[all …]
H A Dbaikal,bt1-ccu-div.yaml5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
15 responsible for the chip subsystems clocking and resetting. The CCU is
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
24 in general can provide any frequency supported by the CCU PLLs).
32 | Baikal-T1 CCU |
50 output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
51 then passed over CCU dividers to create signals required for the target clock
66 where CLKIN is the reference clock coming either from CCU PLLs or from an
77 devices, are united into a single clocks provider called System Devices CCU.
[all …]
/linux/drivers/clk/bcm/
H A Dclk-kona.c17 * CCU. (I believe these polices are named "Deep Sleep", "Economy",
102 /* CCU access */
104 /* Read a 32-bit register value from a CCU's address space. */
105 static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset) in __ccu_read() argument
107 return readl(ccu->base + reg_offset); in __ccu_read()
110 /* Write a 32-bit register value into a CCU's address space. */
112 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) in __ccu_write() argument
114 writel(reg_val, ccu->base + reg_offset); in __ccu_write()
117 static inline unsigned long ccu_lock(struct ccu_data *ccu) in ccu_lock() argument
121 spin_lock_irqsave(&ccu->lock, flags); in ccu_lock()
[all …]
H A Dclk-kona-setup.c18 static bool ccu_data_offsets_valid(struct ccu_data *ccu) in ccu_data_offsets_valid() argument
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
85 range = bcm_clk->ccu->range; in peri_clk_data_offsets_valid()
408 * where we need something from the ccu, so we do these in peri_clk_data_valid()
739 static void ccu_clks_teardown(struct ccu_data *ccu) in ccu_clks_teardown() argument
743 for (i = 0; i < ccu->clk_num; i++) in ccu_clks_teardown()
744 kona_clk_teardown(&ccu->kona_clks[i].hw); in ccu_clks_teardown()
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun6i-a31.dtsi48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
70 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
71 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
72 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
73 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
81 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
82 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
83 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
107 clocks = <&ccu CLK_CPU>;
[all …]
H A Dsunxi-h3-h5.dtsi45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
49 #include <dt-bindings/reset/sun8i-h3-ccu.h>
50 #include <dt-bindings/reset/sun8i-r-ccu.h>
67 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
76 <&ccu CLK_TVE>;
119 clocks = <&ccu CLK_BUS_DE>,
120 <&ccu CLK_DE>;
123 resets = <&ccu RST_BUS_DE>;
155 clocks = <&ccu CLK_BUS_DMA>;
[all …]
H A Dsun4i-a10.dtsi46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
[all …]
H A Dsun8i-r40.dtsi47 #include <dt-bindings/clock/sun8i-r40-ccu.h>
49 #include <dt-bindings/reset/sun8i-r40-ccu.h>
88 clocks = <&ccu CLK_CPU>;
97 clocks = <&ccu CLK_CPU>;
106 clocks = <&ccu CLK_CPU>;
115 clocks = <&ccu CLK_CPU>;
177 clocks = <&ccu CLK_BUS_DE>,
178 <&ccu CLK_DE>;
181 resets = <&ccu RST_BUS_DE>;
234 clocks = <&ccu CLK_BUS_DEINTERLACE>,
[all …]
H A Dsun5i.dtsi45 #include <dt-bindings/clock/sun5i-ccu.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
62 clocks = <&ccu CLK_CPU>;
75 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
76 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
84 clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
85 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
86 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
188 clocks = <&ccu CLK_MBUS>;
199 clocks = <&ccu CLK_AHB_DMA>;
[all …]
H A Dsun8i-v3s.dtsi46 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
47 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
65 <&ccu CLK_TCON0>;
78 clocks = <&ccu CLK_CPU>;
127 clocks = <&ccu CLK_BUS_DE>,
128 <&ccu CLK_DE>;
131 resets = <&ccu RST_BUS_DE>;
181 clocks = <&ccu CLK_BUS_DMA>;
182 resets = <&ccu RST_BUS_DMA>;
190 clocks = <&ccu CLK_BUS_TCON0>,
[all …]
H A Dsun7i-a20.dtsi48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
70 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
71 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
72 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
73 <&ccu CLK_HDMI>;
81 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
82 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
83 <&ccu CLK_DRAM_DE_BE0>;
91 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
[all …]
H A Dsun8i-a23-a33.dtsi48 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
49 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
65 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
66 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
67 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
160 clocks = <&ccu CLK_BUS_DMA>;
161 resets = <&ccu RST_BUS_DMA>;
169 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
171 resets = <&ccu RST_BUS_NAND>;
187 clocks = <&ccu CLK_BUS_LCD>,
[all …]
H A Dsun8i-a83t.dtsi47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
67 clocks = <&ccu CLK_C0CPUX>;
78 clocks = <&ccu CLK_C0CPUX>;
89 clocks = <&ccu CLK_C0CPUX>;
100 clocks = <&ccu CLK_C0CPUX>;
111 clocks = <&ccu CLK_C1CPUX>;
122 clocks = <&ccu CLK_C1CPUX>;
[all …]
H A Dsun8i-h3.dtsi78 clocks = <&ccu CLK_CPUX>;
88 clocks = <&ccu CLK_CPUX>;
98 clocks = <&ccu CLK_CPUX>;
108 clocks = <&ccu CLK_CPUX>;
156 clocks = <&ccu CLK_BUS_DEINTERLACE>,
157 <&ccu CLK_DEINTERLACE>,
158 <&ccu CLK_DRAM_DEINTERLACE>;
160 resets = <&ccu RST_BUS_DEINTERLACE>;
191 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
192 <&ccu CLK_DRAM_VE>;
[all …]
H A Dsun8i-a33.dtsi128 clocks = <&ccu CLK_CPUX>;
135 clocks = <&ccu CLK_CPUX>;
145 clocks = <&ccu CLK_CPUX>;
155 clocks = <&ccu CLK_CPUX>;
209 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
210 <&ccu CLK_DRAM_VE>;
212 resets = <&ccu RST_BUS_VE>;
221 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
223 resets = <&ccu RST_BUS_SS>;
232 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h616.dtsi7 #include <dt-bindings/clock/sun50i-h616-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
10 #include <dt-bindings/reset/sun50i-h616-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
28 clocks = <&ccu CLK_CPUX>;
44 clocks = <&ccu CLK_CPUX>;
60 clocks = <&ccu CLK_CPUX>;
76 clocks = <&ccu CLK_CPUX>;
161 clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>;
164 resets = <&ccu RST_BUS_GPU>;
[all …]
H A Dsun50i-h6.dtsi5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
29 clocks = <&ccu CLK_CPUX>;
45 clocks = <&ccu CLK_CPUX>;
61 clocks = <&ccu CLK_CPUX>;
77 clocks = <&ccu CLK_CPUX>;
156 clocks = <&ccu CLK_BUS_DE>,
157 <&ccu CLK_DE>;
[all …]
H A Dsun50i-a100.dtsi7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
26 clocks = <&ccu CLK_CPUX>;
34 clocks = <&ccu CLK_CPUX>;
42 clocks = <&ccu CLK_CPUX>;
50 clocks = <&ccu CLK_CPUX>;
141 ccu: clock@3001000 { label
142 compatible = "allwinner,sun50i-a100-ccu";
[all …]
H A Dsun50i-h5.dtsi18 clocks = <&ccu CLK_CPUX>;
27 clocks = <&ccu CLK_CPUX>;
36 clocks = <&ccu CLK_CPUX>;
45 clocks = <&ccu CLK_CPUX>;
103 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
104 <&ccu CLK_DRAM_VE>;
106 resets = <&ccu RST_BUS_VE>;
115 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
117 resets = <&ccu RST_BUS_CE>;
123 clocks = <&ccu CLK_BUS_DEINTERLACE>,
[all …]
/linux/include/dt-bindings/clock/
H A Dbcm281xx.h16 * These are the bcm281xx CCU device tree "compatible" strings.
21 #define BCM281XX_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu"
22 #define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
23 #define BCM281XX_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu"
24 #define BCM281XX_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu"
25 #define BCM281XX_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu"
27 /* root CCU clock ids */
32 /* aon CCU clock ids */
39 /* hub CCU clock ids */
44 /* master CCU clock ids */
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-tcon.yaml369 * This comes from the clock/sun4i-a10-ccu.h and
370 * reset/sun4i-a10-ccu.h headers, but we can't include them since
384 resets = <&ccu RST_TCON0>;
386 clocks = <&ccu CLK_AHB_LCD0>,
387 <&ccu CLK_TCON0_CH0>,
388 <&ccu CLK_TCON0_CH1>;
439 * This comes from the clock/sun6i-a31-ccu.h and
440 * reset/sun6i-a31-ccu.h headers, but we can't include them since
457 resets = <&ccu RST_AHB1_LCD0>, <&ccu RST_AHB1_LVDS>;
459 clocks = <&ccu CLK_AHB1_LCD0>,
[all …]

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