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/linux/drivers/gpio/
H A Dgpio-omap.c78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
125 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
126 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
128 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
129 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
[all …]
H A Dgpio-rockchip.c82 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
85 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
87 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
93 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
96 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
99 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
107 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
111 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
114 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit()
129 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument
[all …]
H A Dgpio-brcmstb.c28 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
29 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
30 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
31 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
32 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
33 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
34 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
35 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
36 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
67 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.c62 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
67 if (bank->eint_mask_offset) in exynos_irq_mask()
68 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
70 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
72 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
73 dev_err(bank->gpio_chip.parent, in exynos_irq_mask()
78 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
80 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
82 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
84 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
[all …]
H A Dpinctrl-s3c64xx.c213 * @bank: pin bank related to the domain
217 struct samsung_pin_bank *bank; member
281 struct samsung_pin_bank *bank, int pin) in s3c64xx_irq_set_function() argument
283 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c64xx_irq_set_function()
291 reg = d->virt_base + bank->pctl_offset; in s3c64xx_irq_set_function()
294 /* 4-bit bank type with 2 con regs */ in s3c64xx_irq_set_function()
302 raw_spin_lock_irqsave(&bank->slock, flags); in s3c64xx_irq_set_function()
306 val |= bank->eint_func << shift; in s3c64xx_irq_set_function()
309 raw_spin_unlock_irqrestore(&bank->slock, flags); in s3c64xx_irq_set_function()
318 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_set_mask() local
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_stat() argument
35 return READ_CSR_STAT(csr_base_addr, bank); in read_csr_stat()
[all …]
H A Dadf_gen4_hw_csr_data.h37 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
39 ADF_RING_BUNDLE_SIZE * (bank) + \
41 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
43 ADF_RING_BUNDLE_SIZE * (bank) + \
45 #define READ_CSR_STAT(csr_base_addr, bank) \ argument
47 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_STAT)
48 #define READ_CSR_UO_STAT(csr_base_addr, bank) \ argument
50 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_UO_STAT)
51 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
53 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
[all …]
H A Dadf_transport.c40 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
42 spin_lock(&bank->lock); in adf_reserve_ring()
43 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
44 spin_unlock(&bank->lock); in adf_reserve_ring()
47 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
48 spin_unlock(&bank->lock); in adf_reserve_ring()
52 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
54 spin_lock(&bank->lock); in adf_unreserve_ring()
55 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
56 spin_unlock(&bank->lock); in adf_unreserve_ring()
[all …]
H A Dadf_gen2_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
35 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
[all …]
H A Dadf_gen2_hw_csr_data.h30 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
[all …]
H A Dadf_transport_debug.c51 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
52 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show()
53 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show()
58 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_ring_show()
60 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_ring_show()
62 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
67 seq_printf(sfile, "ring num %d, bank num %d\n", in adf_ring_show()
68 ring->ring_number, ring->bank->bank_number); in adf_ring_show()
111 ring->bank->bank_debug_dir, in adf_ring_debugfs_add()
128 struct adf_etr_bank_data *bank = sfile->private; in adf_bank_start() local
[all …]
/linux/tools/testing/selftests/gpio/
H A Dgpio-sim.sh25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
38 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE || \
43 rmdir $CONFIGFS_DIR/$CHIP/$BANK
57 local BANK=$2
59 mkdir $CONFIGFS_DIR/$CHIP/$BANK
64 local BANK=$2
[all …]
/linux/drivers/pinctrl/renesas/
H A Dsh_pfc.h442 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
443 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
444 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
446 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
447 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
448 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
449 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument
451 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
452 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
453 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json236 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed.",
246 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed.",
256 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
266 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
600 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
605 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
610 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
615 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1
[all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json198 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
208 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
218 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
228 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
553 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
558 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
562 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
567 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
572 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
577 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
[all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json227 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
237 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
247 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
257 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
587 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
601 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
606 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
[all …]
/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32.c184 static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt);
219 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
222 bank->pin_backup[offset].value = value; in stm32_gpio_backup_value()
225 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
228 bank->pin_backup[offset].mode = mode; in stm32_gpio_backup_mode()
229 bank->pin_backup[offset].alt = alt; in stm32_gpio_backup_mode()
232 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
235 bank->pin_backup[offset].drive = drive; in stm32_gpio_backup_driving()
238 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_speed() argument
241 bank->pin_backup[offset].speed = speed; in stm32_gpio_backup_speed()
[all …]
/linux/drivers/net/phy/mscc/
H A Dmscc_macsec.c23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write()
75 bank &= 0x3; in vsc8584_macsec_phy_write()
[all …]
/linux/drivers/bus/
H A Duniphier-system-bus.c23 #define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
25 #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff /* data to squash bank 0, 1 */
35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
44 "range found: bank = %d, addr = %08x, paddr = %08llx, size = %08x\n", in uniphier_system_bus_add_bank()
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
52 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank()
54 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank()
[all …]
/linux/arch/x86/kernel/cpu/mce/
H A Damd.c141 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
145 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
148 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
222 * So to define a unique name for each bank, we use a temp c-string to append
232 /* This block's number within its bank. */
234 /* MCA bank number that contains this block. */
235 unsigned int bank; member
236 /* CPU which controls this block's MCA bank. */
242 /* Bank can generate an interrupt. */
248 /* List of threshold blocks within this block's MCA bank. */
[all …]
H A Dintel.c31 * CMCI can be delivered to multiple cpus that share a machine check bank
32 * so we need to designate a single cpu to process errors logged in each bank
61 * MCi_CTL2 threshold for each bank when there is no storm.
62 * Default value for each bank may have been set by BIOS.
71 * bank because both corrected and uncorrected errors may be logged
72 * in the same bank and signalled with CMCI. The threshold only applies
138 static void cmci_set_threshold(int bank, int thresh) in cmci_set_threshold() argument
144 rdmsrq(MSR_IA32_MCx_CTL2(bank), val); in cmci_set_threshold()
146 wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh); in cmci_set_threshold()
150 void mce_intel_handle_storm(int bank, bool on) in mce_intel_handle_storm() argument
[all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json263 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
274 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
285 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
296 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
653 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
662 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
672 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
682 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
692 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
702 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
[all …]
/linux/drivers/gpu/drm/amd/ras/rascore/
H A Dras_aca_v1_0.c41 struct aca_bank_reg *bank, struct aca_ecc_info *info) in aca_decode_bank_info() argument
46 ipid = bank->regs[ACA_REG_IDX__IPID]; in aca_decode_bank_info()
67 static bool aca_check_bank_hwip(struct aca_bank_reg *bank, enum aca_ecc_hwip type) in aca_check_bank_hwip() argument
73 if (!bank || (type == ACA_ECC_HWIP__UNKNOWN)) in aca_check_bank_hwip()
80 ipid = bank->regs[ACA_REG_IDX__IPID]; in aca_check_bank_hwip()
94 struct aca_bank_reg *bank = (struct aca_bank_reg *)data; in aca_match_gfx_bank() local
97 if (!aca_check_bank_hwip(bank, aca_blk->blk_info->hwip)) in aca_match_gfx_bank()
100 instlo = ACA_REG_IPID_INSTANCEIDLO(bank->regs[ACA_REG_IDX__IPID]); in aca_match_gfx_bank()
116 struct aca_bank_reg *bank = (struct aca_bank_reg *)data; in aca_match_sdma_bank() local
122 if (!aca_check_bank_hwip(bank, aca_blk->blk_info->hwip)) in aca_match_sdma_bank()
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-rockchip.c331 * given a pin number that is local to a pin controller, find out the pin bank
332 * and the register base of the pin bank.
775 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
778 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
785 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
1122 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
1125 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1132 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1147 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
1149 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
[all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-memory.json281 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
292 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
303 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
314 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
1029 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
1038 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
1048 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
1058 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
1068 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
1078 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
[all …]

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