Lines Matching full:bank
62 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
67 if (bank->eint_mask_offset) in exynos_irq_mask()
68 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
70 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
72 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
73 dev_err(bank->gpio_chip.parent, in exynos_irq_mask()
78 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
80 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
82 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
84 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
86 clk_disable(bank->drvdata->pclk); in exynos_irq_mask()
93 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_ack() local
96 if (bank->eint_pend_offset) in exynos_irq_ack()
97 reg_pend = bank->pctl_offset + bank->eint_pend_offset; in exynos_irq_ack()
99 reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
101 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_ack()
102 dev_err(bank->gpio_chip.parent, in exynos_irq_ack()
107 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
109 clk_disable(bank->drvdata->pclk); in exynos_irq_ack()
116 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_unmask() local
132 if (bank->eint_mask_offset) in exynos_irq_unmask()
133 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_unmask()
135 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_unmask()
137 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_unmask()
138 dev_err(bank->gpio_chip.parent, in exynos_irq_unmask()
143 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_unmask()
145 mask = readl(bank->eint_base + reg_mask); in exynos_irq_unmask()
147 writel(mask, bank->eint_base + reg_mask); in exynos_irq_unmask()
149 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_unmask()
151 clk_disable(bank->drvdata->pclk); in exynos_irq_unmask()
158 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_set_type() local
190 if (bank->eint_con_offset) in exynos_irq_set_type()
191 reg_con = bank->pctl_offset + bank->eint_con_offset; in exynos_irq_set_type()
193 reg_con = our_chip->eint_con + bank->eint_offset; in exynos_irq_set_type()
195 ret = clk_enable(bank->drvdata->pclk); in exynos_irq_set_type()
197 dev_err(bank->gpio_chip.parent, in exynos_irq_set_type()
202 con = readl(bank->eint_base + reg_con); in exynos_irq_set_type()
205 writel(con, bank->eint_base + reg_con); in exynos_irq_set_type()
207 clk_disable(bank->drvdata->pclk); in exynos_irq_set_type()
215 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_set_affinity() local
216 struct samsung_pinctrl_drv_data *d = bank->drvdata; in exynos_irq_set_affinity()
227 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_request_resources() local
228 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_request_resources()
233 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_request_resources()
235 dev_err(bank->gpio_chip.parent, in exynos_irq_request_resources()
237 bank->name, irqd->hwirq); in exynos_irq_request_resources()
241 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_request_resources()
245 ret = clk_enable(bank->drvdata->pclk); in exynos_irq_request_resources()
247 dev_err(bank->gpio_chip.parent, in exynos_irq_request_resources()
249 bank->name, irqd->hwirq); in exynos_irq_request_resources()
253 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_request_resources()
255 con = readl(bank->pctl_base + reg_con); in exynos_irq_request_resources()
258 writel(con, bank->pctl_base + reg_con); in exynos_irq_request_resources()
260 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_request_resources()
262 clk_disable(bank->drvdata->pclk); in exynos_irq_request_resources()
269 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_release_resources() local
270 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_release_resources()
274 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_release_resources()
278 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_release_resources()
279 dev_err(bank->gpio_chip.parent, in exynos_irq_release_resources()
281 bank->name, irqd->hwirq); in exynos_irq_release_resources()
285 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_release_resources()
287 con = readl(bank->pctl_base + reg_con); in exynos_irq_release_resources()
290 writel(con, bank->pctl_base + reg_con); in exynos_irq_release_resources()
292 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_release_resources()
294 clk_disable(bank->drvdata->pclk); in exynos_irq_release_resources()
296 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_release_resources()
341 struct samsung_pin_bank *bank = d->pin_banks; in exynos_eint_gpio_irq() local
345 if (clk_enable(bank->drvdata->pclk)) { in exynos_eint_gpio_irq()
346 dev_err(bank->gpio_chip.parent, in exynos_eint_gpio_irq()
351 if (bank->eint_con_offset) in exynos_eint_gpio_irq()
352 svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET); in exynos_eint_gpio_irq()
354 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); in exynos_eint_gpio_irq()
356 clk_disable(bank->drvdata->pclk); in exynos_eint_gpio_irq()
363 bank += (group - 1); in exynos_eint_gpio_irq()
365 ret = generic_handle_domain_irq(bank->irq_domain, pin); in exynos_eint_gpio_irq()
395 * every pin in the bank. Note the filter selection bitfield is only
399 static void exynos_eint_set_filter(struct samsung_pin_bank *bank, int filter) in exynos_eint_set_filter() argument
401 unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->eint_fltcon_offset; in exynos_eint_set_filter()
402 void __iomem *reg = bank->drvdata->virt_base + off; in exynos_eint_set_filter()
405 for (int n = 0; n < bank->nr_pins; n += 4) in exynos_eint_set_filter()
407 min(bank->nr_pins - n, 4), con); in exynos_eint_set_filter()
416 struct samsung_pin_bank *bank; in exynos_eint_gpio_init() local
433 bank = d->pin_banks; in exynos_eint_gpio_init()
434 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_gpio_init()
435 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
438 bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip, in exynos_eint_gpio_init()
439 sizeof(*bank->irq_chip), GFP_KERNEL); in exynos_eint_gpio_init()
440 if (!bank->irq_chip) { in exynos_eint_gpio_init()
444 bank->irq_chip->chip.name = bank->name; in exynos_eint_gpio_init()
446 bank->irq_domain = irq_domain_create_linear(bank->fwnode, in exynos_eint_gpio_init()
447 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_gpio_init()
448 if (!bank->irq_domain) { in exynos_eint_gpio_init()
454 bank->soc_priv = devm_kzalloc(d->dev, in exynos_eint_gpio_init()
456 if (!bank->soc_priv) { in exynos_eint_gpio_init()
457 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
467 for (--i, --bank; i >= 0; --i, --bank) { in exynos_eint_gpio_init()
468 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
470 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
479 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in gs101_wkup_irq_set_wake() local
480 struct samsung_pinctrl_drv_data *d = bank->drvdata; in gs101_wkup_irq_set_wake()
483 bit = bank->eint_num + irqd->hwirq; in gs101_wkup_irq_set_wake()
525 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_wkup_irq_set_wake() local
526 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); in exynos_wkup_irq_set_wake()
529 irqd->irq, bank->name, irqd->hwirq); in exynos_wkup_irq_set_wake()
547 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in exynos_pinctrl_set_eint_wakeup_mask()
569 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in s5pv210_pinctrl_set_eint_wakeup_mask()
699 struct samsung_pin_bank *bank = eintd->bank; in exynos_irq_eint0_15() local
704 generic_handle_domain_irq(bank->irq_domain, eintd->irq); in exynos_irq_eint0_15()
734 * each bank. in exynos_irq_demux_eint16_31()
772 struct samsung_pin_bank *bank; in exynos_eint_wkup_init() local
793 bank = d->pin_banks; in exynos_eint_wkup_init()
794 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
795 if (bank->eint_type != EINT_TYPE_WKUP) in exynos_eint_wkup_init()
798 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), in exynos_eint_wkup_init()
800 if (!bank->irq_chip) in exynos_eint_wkup_init()
802 bank->irq_chip->chip.name = bank->name; in exynos_eint_wkup_init()
804 bank->irq_domain = irq_domain_create_linear(bank->fwnode, in exynos_eint_wkup_init()
805 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_wkup_init()
806 if (!bank->irq_domain) { in exynos_eint_wkup_init()
811 bank->eint_num = eint_num; in exynos_eint_wkup_init()
812 eint_num = eint_num + bank->nr_pins; in exynos_eint_wkup_init()
814 if (!fwnode_property_present(bank->fwnode, "interrupts")) { in exynos_eint_wkup_init()
815 bank->eint_type = EINT_TYPE_WKUP_MUX; in exynos_eint_wkup_init()
821 bank->nr_pins, sizeof(*weint_data), in exynos_eint_wkup_init()
826 for (idx = 0; idx < bank->nr_pins; ++idx) { in exynos_eint_wkup_init()
827 irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx); in exynos_eint_wkup_init()
830 bank->name, idx); in exynos_eint_wkup_init()
834 weint_data[idx].bank = bank; in exynos_eint_wkup_init()
859 bank = d->pin_banks; in exynos_eint_wkup_init()
861 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
862 if (bank->eint_type != EINT_TYPE_WKUP_MUX) in exynos_eint_wkup_init()
865 muxed_data->banks[idx++] = bank; in exynos_eint_wkup_init()
871 static void exynos_set_wakeup(struct samsung_pin_bank *bank) in exynos_set_wakeup() argument
875 if (bank->irq_chip) { in exynos_set_wakeup()
876 irq_chip = bank->irq_chip; in exynos_set_wakeup()
877 irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip); in exynos_set_wakeup()
881 void exynos_pinctrl_suspend(struct samsung_pin_bank *bank) in exynos_pinctrl_suspend() argument
883 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_suspend()
884 const void __iomem *regs = bank->eint_base; in exynos_pinctrl_suspend()
886 if (bank->eint_type == EINT_TYPE_GPIO) { in exynos_pinctrl_suspend()
888 + bank->eint_offset); in exynos_pinctrl_suspend()
890 + 2 * bank->eint_offset); in exynos_pinctrl_suspend()
892 + 2 * bank->eint_offset + 4); in exynos_pinctrl_suspend()
893 save->eint_mask = readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_suspend()
894 + bank->eint_offset); in exynos_pinctrl_suspend()
897 bank->name, save->eint_con); in exynos_pinctrl_suspend()
899 bank->name, save->eint_fltcon0); in exynos_pinctrl_suspend()
901 bank->name, save->eint_fltcon1); in exynos_pinctrl_suspend()
903 bank->name, save->eint_mask); in exynos_pinctrl_suspend()
904 } else if (bank->eint_type == EINT_TYPE_WKUP) { in exynos_pinctrl_suspend()
905 exynos_set_wakeup(bank); in exynos_pinctrl_suspend()
909 void gs101_pinctrl_suspend(struct samsung_pin_bank *bank) in gs101_pinctrl_suspend() argument
911 struct exynos_eint_gpio_save *save = bank->soc_priv; in gs101_pinctrl_suspend()
912 const void __iomem *regs = bank->eint_base; in gs101_pinctrl_suspend()
914 if (bank->eint_type == EINT_TYPE_GPIO) { in gs101_pinctrl_suspend()
916 + bank->eint_offset); in gs101_pinctrl_suspend()
919 + bank->eint_fltcon_offset); in gs101_pinctrl_suspend()
922 if (bank->nr_pins > 4) in gs101_pinctrl_suspend()
925 + bank->eint_fltcon_offset + 4); in gs101_pinctrl_suspend()
927 save->eint_mask = readl(regs + bank->irq_chip->eint_mask in gs101_pinctrl_suspend()
928 + bank->eint_offset); in gs101_pinctrl_suspend()
931 bank->name, save->eint_con); in gs101_pinctrl_suspend()
933 bank->name, save->eint_fltcon0); in gs101_pinctrl_suspend()
934 if (bank->nr_pins > 4) in gs101_pinctrl_suspend()
936 bank->name, save->eint_fltcon1); in gs101_pinctrl_suspend()
938 bank->name, save->eint_mask); in gs101_pinctrl_suspend()
939 } else if (bank->eint_type == EINT_TYPE_WKUP) { in gs101_pinctrl_suspend()
940 exynos_set_wakeup(bank); in gs101_pinctrl_suspend()
941 exynos_eint_set_filter(bank, EXYNOS_FLTCON_ANALOG); in gs101_pinctrl_suspend()
945 void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) in exynosautov920_pinctrl_suspend() argument
947 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynosautov920_pinctrl_suspend()
948 const void __iomem *regs = bank->eint_base; in exynosautov920_pinctrl_suspend()
950 if (bank->eint_type == EINT_TYPE_GPIO) { in exynosautov920_pinctrl_suspend()
951 save->eint_con = readl(regs + bank->pctl_offset + in exynosautov920_pinctrl_suspend()
952 bank->eint_con_offset); in exynosautov920_pinctrl_suspend()
953 save->eint_mask = readl(regs + bank->pctl_offset + in exynosautov920_pinctrl_suspend()
954 bank->eint_mask_offset); in exynosautov920_pinctrl_suspend()
956 bank->name, save->eint_con); in exynosautov920_pinctrl_suspend()
958 bank->name, save->eint_mask); in exynosautov920_pinctrl_suspend()
959 } else if (bank->eint_type == EINT_TYPE_WKUP) { in exynosautov920_pinctrl_suspend()
960 exynos_set_wakeup(bank); in exynosautov920_pinctrl_suspend()
964 void gs101_pinctrl_resume(struct samsung_pin_bank *bank) in gs101_pinctrl_resume() argument
966 struct exynos_eint_gpio_save *save = bank->soc_priv; in gs101_pinctrl_resume()
968 void __iomem *regs = bank->eint_base; in gs101_pinctrl_resume()
970 + bank->eint_fltcon_offset; in gs101_pinctrl_resume()
972 if (bank->eint_type == EINT_TYPE_GPIO) { in gs101_pinctrl_resume()
973 pr_debug("%s: con %#010x => %#010x\n", bank->name, in gs101_pinctrl_resume()
975 + bank->eint_offset), save->eint_con); in gs101_pinctrl_resume()
977 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, in gs101_pinctrl_resume()
981 if (bank->nr_pins > 4) in gs101_pinctrl_resume()
982 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, in gs101_pinctrl_resume()
985 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in gs101_pinctrl_resume()
986 readl(regs + bank->irq_chip->eint_mask in gs101_pinctrl_resume()
987 + bank->eint_offset), save->eint_mask); in gs101_pinctrl_resume()
990 + bank->eint_offset); in gs101_pinctrl_resume()
993 if (bank->nr_pins > 4) in gs101_pinctrl_resume()
995 writel(save->eint_mask, regs + bank->irq_chip->eint_mask in gs101_pinctrl_resume()
996 + bank->eint_offset); in gs101_pinctrl_resume()
997 } else if (bank->eint_type == EINT_TYPE_WKUP) { in gs101_pinctrl_resume()
998 exynos_eint_set_filter(bank, EXYNOS_FLTCON_DIGITAL); in gs101_pinctrl_resume()
1002 void exynos_pinctrl_resume(struct samsung_pin_bank *bank) in exynos_pinctrl_resume() argument
1004 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_resume()
1005 void __iomem *regs = bank->eint_base; in exynos_pinctrl_resume()
1007 if (bank->eint_type == EINT_TYPE_GPIO) { in exynos_pinctrl_resume()
1008 pr_debug("%s: con %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume()
1010 + bank->eint_offset), save->eint_con); in exynos_pinctrl_resume()
1011 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume()
1013 + 2 * bank->eint_offset), save->eint_fltcon0); in exynos_pinctrl_resume()
1014 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume()
1016 + 2 * bank->eint_offset + 4), in exynos_pinctrl_resume()
1018 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume()
1019 readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume()
1020 + bank->eint_offset), save->eint_mask); in exynos_pinctrl_resume()
1023 + bank->eint_offset); in exynos_pinctrl_resume()
1025 + 2 * bank->eint_offset); in exynos_pinctrl_resume()
1027 + 2 * bank->eint_offset + 4); in exynos_pinctrl_resume()
1028 writel(save->eint_mask, regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume()
1029 + bank->eint_offset); in exynos_pinctrl_resume()
1033 void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank) in exynosautov920_pinctrl_resume() argument
1035 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynosautov920_pinctrl_resume()
1036 void __iomem *regs = bank->eint_base; in exynosautov920_pinctrl_resume()
1038 if (bank->eint_type == EINT_TYPE_GPIO) { in exynosautov920_pinctrl_resume()
1039 /* exynosautov920 has eint_con_offset for all but one bank */ in exynosautov920_pinctrl_resume()
1040 if (!bank->eint_con_offset) in exynosautov920_pinctrl_resume()
1041 exynos_pinctrl_resume(bank); in exynosautov920_pinctrl_resume()
1043 pr_debug("%s: con %#010x => %#010x\n", bank->name, in exynosautov920_pinctrl_resume()
1044 readl(regs + bank->pctl_offset + bank->eint_con_offset), in exynosautov920_pinctrl_resume()
1046 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in exynosautov920_pinctrl_resume()
1047 readl(regs + bank->pctl_offset + in exynosautov920_pinctrl_resume()
1048 bank->eint_mask_offset), save->eint_mask); in exynosautov920_pinctrl_resume()
1051 regs + bank->pctl_offset + bank->eint_con_offset); in exynosautov920_pinctrl_resume()
1053 regs + bank->pctl_offset + bank->eint_mask_offset); in exynosautov920_pinctrl_resume()