141 static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt);
176 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,  in stm32_gpio_backup_value()  argument
179 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);  in stm32_gpio_backup_value()
180 	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;  in stm32_gpio_backup_value()
183 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_mode()  argument
186 	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |  in stm32_gpio_backup_mode()
188 	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;  in stm32_gpio_backup_mode()
189 	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;  in stm32_gpio_backup_mode()
192 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_driving()  argument
195 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);  in stm32_gpio_backup_driving()
196 	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;  in stm32_gpio_backup_driving()
199 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_speed()  argument
202 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;  in stm32_gpio_backup_speed()
203 	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;  in stm32_gpio_backup_speed()
206 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_bias()  argument
209 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;  in stm32_gpio_backup_bias()
210 	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;  in stm32_gpio_backup_bias()
215 static bool stm32_gpio_rif_valid(struct stm32_gpio_bank *bank, unsigned int gpio_nr)  in stm32_gpio_rif_valid()  argument
219 	cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));  in stm32_gpio_rif_valid()
237 static bool stm32_gpio_rif_acquire_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)  in stm32_gpio_rif_acquire_semaphore()  argument
241 	cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));  in stm32_gpio_rif_acquire_semaphore()
256 	sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));  in stm32_gpio_rif_acquire_semaphore()
264 	writel_relaxed(STM32_GPIO_SEMCR_SEM_MUTEX, bank->base + STM32_GPIO_SEMCR(gpio_nr));  in stm32_gpio_rif_acquire_semaphore()
266 	sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));  in stm32_gpio_rif_acquire_semaphore()
274 static void stm32_gpio_rif_release_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)  in stm32_gpio_rif_release_semaphore()  argument
278 	cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));  in stm32_gpio_rif_release_semaphore()
284 		writel_relaxed(0, bank->base + STM32_GPIO_SEMCR(gpio_nr));  in stm32_gpio_rif_release_semaphore()
289 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,  in __stm32_gpio_set()  argument
292 	stm32_gpio_backup_value(bank, offset, value);  in __stm32_gpio_set()
297 	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);  in __stm32_gpio_set()
302 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_request()  local
303 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_request()
305 	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);  in stm32_gpio_request()
313 	if (bank->rif_control) {  in stm32_gpio_request()
314 		if (!stm32_gpio_rif_acquire_semaphore(bank, offset)) {  in stm32_gpio_request()
325 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_free()  local
329 	if (bank->rif_control)  in stm32_gpio_free()
330 		stm32_gpio_rif_release_semaphore(bank, offset);  in stm32_gpio_free()
335 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_get()  local
337 	return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));  in stm32_gpio_get()
343 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_set()  local
345 	__stm32_gpio_set(bank, offset, value);  in stm32_gpio_set()
353 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_direction_output()  local
355 	__stm32_gpio_set(bank, offset, value);  in stm32_gpio_direction_output()
363 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_to_irq()  local
366 	fwspec.fwnode = bank->fwnode;  in stm32_gpio_to_irq()
376 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_get_direction()  local
381 	stm32_pmx_get_mode(bank, pin, &mode, &alt);  in stm32_gpio_get_direction()
396 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_init_valid_mask()  local
397 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_init_valid_mask()
404 	if (bank->secure_control) {  in stm32_gpio_init_valid_mask()
406 		sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);  in stm32_gpio_init_valid_mask()
411 				dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);  in stm32_gpio_init_valid_mask()
416 	if (bank->rif_control) {  in stm32_gpio_init_valid_mask()
421 			if (stm32_gpio_rif_valid(bank, i))  in stm32_gpio_init_valid_mask()
447 	struct stm32_gpio_bank *bank = d->domain->host_data;  in stm32_gpio_irq_trigger()  local
451 	if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))  in stm32_gpio_irq_trigger()
455 	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);  in stm32_gpio_irq_trigger()
456 	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||  in stm32_gpio_irq_trigger()
457 	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))  in stm32_gpio_irq_trigger()
469 	struct stm32_gpio_bank *bank = d->domain->host_data;  in stm32_gpio_set_type()  local
488 	bank->irq_type[d->hwirq] = type;  in stm32_gpio_set_type()
495 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;  in stm32_gpio_irq_request_resources()  local
496 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_irq_request_resources()
499 	ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_request_resources()
503 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_request_resources()
515 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;  in stm32_gpio_irq_release_resources()  local
517 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_release_resources()
556 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_activate()  local
557 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_activate()
569 	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);  in stm32_gpio_domain_activate()
581 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_alloc()  local
584 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_alloc()
612 				      bank);  in stm32_gpio_domain_alloc()
620 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_free()  local
621 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_free()
885 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,  in stm32_pmx_set_mode()  argument
888 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pmx_set_mode()
895 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pmx_set_mode()
906 	val = readl_relaxed(bank->base + alt_offset);  in stm32_pmx_set_mode()
909 	writel_relaxed(val, bank->base + alt_offset);  in stm32_pmx_set_mode()
911 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);  in stm32_pmx_set_mode()
914 	writel_relaxed(val, bank->base + STM32_GPIO_MODER);  in stm32_pmx_set_mode()
919 	stm32_gpio_backup_mode(bank, pin, mode, alt);  in stm32_pmx_set_mode()
922 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pmx_set_mode()
927 static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt)  in stm32_pmx_get_mode()  argument
934 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pmx_get_mode()
936 	val = readl_relaxed(bank->base + alt_offset);  in stm32_pmx_get_mode()
940 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);  in stm32_pmx_get_mode()
944 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pmx_get_mode()
955 	struct stm32_gpio_bank *bank;  in stm32_pmx_set_mux()  local
974 	bank = gpiochip_get_data(range->gc);  in stm32_pmx_set_mux()
980 	return stm32_pmx_set_mode(bank, pin, mode, alt);  in stm32_pmx_set_mux()
987 	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);  in stm32_pmx_gpio_set_direction()  local
990 	return stm32_pmx_set_mode(bank, pin, !input, 0);  in stm32_pmx_gpio_set_direction()
1024 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,  in stm32_pconf_set_driving()  argument
1027 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_driving()
1032 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_driving()
1043 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);  in stm32_pconf_set_driving()
1046 	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);  in stm32_pconf_set_driving()
1051 	stm32_gpio_backup_driving(bank, offset, drive);  in stm32_pconf_set_driving()
1054 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_driving()
1059 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,  in stm32_pconf_get_driving()  argument
1065 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_driving()
1067 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);  in stm32_pconf_get_driving()
1070 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_driving()
1075 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,  in stm32_pconf_set_speed()  argument
1078 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_speed()
1083 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_speed()
1094 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_set_speed()
1097 	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_set_speed()
1102 	stm32_gpio_backup_speed(bank, offset, speed);  in stm32_pconf_set_speed()
1105 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_speed()
1110 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,  in stm32_pconf_get_speed()  argument
1116 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_speed()
1118 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_get_speed()
1121 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_speed()
1126 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,  in stm32_pconf_set_bias()  argument
1129 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_bias()
1134 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_bias()
1145 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_set_bias()
1148 	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_set_bias()
1153 	stm32_gpio_backup_bias(bank, offset, bias);  in stm32_pconf_set_bias()
1156 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_bias()
1161 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,  in stm32_pconf_get_bias()  argument
1167 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_bias()
1169 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_get_bias()
1172 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_bias()
1177 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,  in stm32_pconf_get()  argument
1183 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get()
1186 		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &  in stm32_pconf_get()
1189 		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &  in stm32_pconf_get()
1192 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get()
1203 	struct stm32_gpio_bank *bank;  in stm32_pconf_parse_conf()  local
1212 	bank = gpiochip_get_data(range->gc);  in stm32_pconf_parse_conf()
1222 		ret = stm32_pconf_set_driving(bank, offset, 0);  in stm32_pconf_parse_conf()
1225 		ret = stm32_pconf_set_driving(bank, offset, 1);  in stm32_pconf_parse_conf()
1228 		ret = stm32_pconf_set_speed(bank, offset, arg);  in stm32_pconf_parse_conf()
1231 		ret = stm32_pconf_set_bias(bank, offset, 0);  in stm32_pconf_parse_conf()
1234 		ret = stm32_pconf_set_bias(bank, offset, 1);  in stm32_pconf_parse_conf()
1237 		ret = stm32_pconf_set_bias(bank, offset, 2);  in stm32_pconf_parse_conf()
1240 		__stm32_gpio_set(bank, offset, arg);  in stm32_pconf_parse_conf()
1321 	struct stm32_gpio_bank *bank;  in stm32_pconf_dbg_show()  local
1336 	bank = gpiochip_get_data(range->gc);  in stm32_pconf_dbg_show()
1344 	stm32_pmx_get_mode(bank, offset, &mode, &alt);  in stm32_pconf_dbg_show()
1345 	bias = stm32_pconf_get_bias(bank, offset);  in stm32_pconf_dbg_show()
1352 		val = stm32_pconf_get(bank, offset, true);  in stm32_pconf_dbg_show()
1360 		drive = stm32_pconf_get_driving(bank, offset);  in stm32_pconf_dbg_show()
1361 		speed = stm32_pconf_get_speed(bank, offset);  in stm32_pconf_dbg_show()
1362 		val = stm32_pconf_get(bank, offset, false);  in stm32_pconf_dbg_show()
1372 		drive = stm32_pconf_get_driving(bank, offset);  in stm32_pconf_dbg_show()
1373 		speed = stm32_pconf_get_speed(bank, offset);  in stm32_pconf_dbg_show()
1399 								 struct stm32_gpio_bank *bank,  in stm32_pctrl_get_desc_pin_from_gpio()  argument
1402 	unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset;  in stm32_pctrl_get_desc_pin_from_gpio()
1406 	/* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */  in stm32_pctrl_get_desc_pin_from_gpio()
1424 	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];  in stm32_gpiolib_register_bank()  local
1426 	struct pinctrl_gpio_range *range = &bank->range;  in stm32_gpiolib_register_bank()
1435 	if (!IS_ERR(bank->rstc))  in stm32_gpiolib_register_bank()
1436 		reset_control_deassert(bank->rstc);  in stm32_gpiolib_register_bank()
1441 	bank->base = devm_ioremap_resource(dev, &res);  in stm32_gpiolib_register_bank()
1442 	if (IS_ERR(bank->base))  in stm32_gpiolib_register_bank()
1443 		return PTR_ERR(bank->base);  in stm32_gpiolib_register_bank()
1445 	bank->gpio_chip = stm32_gpio_template;  in stm32_gpiolib_register_bank()
1447 	fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);  in stm32_gpiolib_register_bank()
1451 		bank->gpio_chip.base = args.args[1];  in stm32_gpiolib_register_bank()
1459 		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;  in stm32_gpiolib_register_bank()
1460 		range->name = bank->gpio_chip.label;  in stm32_gpiolib_register_bank()
1465 		range->gc = &bank->gpio_chip;  in stm32_gpiolib_register_bank()
1470 	if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))  in stm32_gpiolib_register_bank()
1473 	bank->gpio_chip.base = -1;  in stm32_gpiolib_register_bank()
1475 	bank->gpio_chip.ngpio = npins;  in stm32_gpiolib_register_bank()
1476 	bank->gpio_chip.fwnode = fwnode;  in stm32_gpiolib_register_bank()
1477 	bank->gpio_chip.parent = dev;  in stm32_gpiolib_register_bank()
1478 	bank->bank_nr = bank_nr;  in stm32_gpiolib_register_bank()
1479 	bank->bank_ioport_nr = bank_ioport_nr;  in stm32_gpiolib_register_bank()
1480 	bank->secure_control = pctl->match_data->secure_control;  in stm32_gpiolib_register_bank()
1481 	bank->rif_control = pctl->match_data->rif_control;  in stm32_gpiolib_register_bank()
1482 	spin_lock_init(&bank->lock);  in stm32_gpiolib_register_bank()
1486 		bank->fwnode = fwnode;  in stm32_gpiolib_register_bank()
1488 		bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,  in stm32_gpiolib_register_bank()
1489 							   bank->fwnode, &stm32_gpio_domain_ops,  in stm32_gpiolib_register_bank()
1490 							   bank);  in stm32_gpiolib_register_bank()
1492 		if (!bank->domain)  in stm32_gpiolib_register_bank()
1501 		stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);  in stm32_gpiolib_register_bank()
1511 	bank->gpio_chip.names = (const char * const *)names;  in stm32_gpiolib_register_bank()
1513 	err = gpiochip_add_data(&bank->gpio_chip, bank);  in stm32_gpiolib_register_bank()
1519 	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);  in stm32_gpiolib_register_bank()
1735 		dev_err(dev, "at least one GPIO bank is required\n");  in stm32_pctl_probe()
1750 		struct stm32_gpio_bank *bank = &pctl->banks[i];  in stm32_pctl_probe()  local
1753 		bank->rstc = of_reset_control_get_exclusive(np, NULL);  in stm32_pctl_probe()
1754 		if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {  in stm32_pctl_probe()
1790 		struct stm32_gpio_bank *bank = &pctl->banks[i];  in stm32_pctl_probe()  local
1792 		gpiochip_remove(&bank->gpio_chip);  in stm32_pctl_probe()
1806 	struct stm32_gpio_bank *bank;  in stm32_pinctrl_restore_gpio_regs()  local
1822 	bank = gpiochip_get_data(range->gc);  in stm32_pinctrl_restore_gpio_regs()
1824 	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;  in stm32_pinctrl_restore_gpio_regs()
1826 	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;  in stm32_pinctrl_restore_gpio_regs()
1829 	ret = stm32_pmx_set_mode(bank, offset, mode, alt);  in stm32_pinctrl_restore_gpio_regs()
1834 		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);  in stm32_pinctrl_restore_gpio_regs()
1836 		__stm32_gpio_set(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1839 	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);  in stm32_pinctrl_restore_gpio_regs()
1841 	ret = stm32_pconf_set_driving(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1845 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;  in stm32_pinctrl_restore_gpio_regs()
1847 	ret = stm32_pconf_set_speed(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1851 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;  in stm32_pinctrl_restore_gpio_regs()
1853 	ret = stm32_pconf_set_bias(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1858 		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);  in stm32_pinctrl_restore_gpio_regs()