| /linux/drivers/staging/fbtft/ |
| H A D | fb_hx8353d.c | 83 * rgb/bgr: in set_var()
85 * rgb h/w pin for color filter setting: 0=rgb, 1=bgr in set_var()
87 * rgb-bgr order color filter panel: 0=rgb, 1=bgr in set_var()
92 mx | my | (par->bgr << 3)); in set_var()
96 my | mv | (par->bgr << 3)); in set_var()
100 par->bgr << 3); in set_var()
104 mx | mv | (par->bgr << 3)); in set_var()
|
| H A D | fb_st7735r.c | 103 * RGB/BGR: in set_var()
105 * RGB H/W pin for color filter setting: 0=RGB, 1=BGR in set_var()
107 * RGB-BGR ORDER color filter panel: 0=RGB, 1=BGR in set_var()
112 MX | MY | (par->bgr << 3)); in set_var()
116 MY | MV | (par->bgr << 3)); in set_var()
120 par->bgr << 3); in set_var()
124 MX | MV | (par->bgr << 3)); in set_var()
|
| H A D | fb_s6d02a1.c | 118 * RGB/BGR: in set_var()
120 * RGB H/W pin for color filter setting: 0=RGB, 1=BGR in set_var()
122 * RGB-BGR ORDER color filter panel: 0=RGB, 1=BGR in set_var()
127 MX | MY | (par->bgr << 3)); in set_var()
131 MY | MV | (par->bgr << 3)); in set_var()
135 par->bgr << 3); in set_var()
139 MX | MV | (par->bgr << 3)); in set_var()
|
| H A D | fb_ili9481.c | 64 ROW_X_COL | HFLIP | VFLIP | (par->bgr << 3)); in set_var()
68 VFLIP | (par->bgr << 3)); in set_var()
72 ROW_X_COL | (par->bgr << 3)); in set_var()
76 HFLIP | (par->bgr << 3)); in set_var()
|
| H A D | fb_ili9486.c | 62 0x80 | (par->bgr << 3)); in set_var()
66 0x20 | (par->bgr << 3)); in set_var()
70 0x40 | (par->bgr << 3)); in set_var()
74 0xE0 | (par->bgr << 3)); in set_var()
|
| H A D | fb_hx8340bn.c | 119 /* RGB/BGR can be set with H/W pin SRGB and MADCTL BGR bit */ in set_var()
125 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, par->bgr << 3); in set_var()
129 MX | MV | (par->bgr << 3)); in set_var()
133 MX | MY | (par->bgr << 3)); in set_var()
137 MY | MV | (par->bgr << 3)); in set_var()
|
| H A D | fb_ili9341.c | 84 #define MEM_BGR (3) /* RGB-BGR Order */
90 MEM_X | (par->bgr << MEM_BGR)); in set_var()
94 MEM_V | MEM_L | (par->bgr << MEM_BGR)); in set_var()
98 MEM_Y | (par->bgr << MEM_BGR)); in set_var()
102 MEM_Y | MEM_X | MEM_V | (par->bgr << MEM_BGR)); in set_var()
|
| H A D | fb_hx8347d.c | 91 #define MEM_BGR (3) /* RGB-BGR Order */
96 write_reg(par, 0x16, MEM_V | MEM_X | (par->bgr << MEM_BGR)); in set_var()
99 write_reg(par, 0x16, par->bgr << MEM_BGR); in set_var()
102 write_reg(par, 0x16, MEM_V | MEM_Y | (par->bgr << MEM_BGR)); in set_var()
105 write_reg(par, 0x16, MEM_X | MEM_Y | (par->bgr << MEM_BGR)); in set_var()
|
| H A D | fb_s6d1121.c | 98 write_reg(par, 0x03, 0x0003 | (par->bgr << 12)); in set_var()
101 write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); in set_var()
104 write_reg(par, 0x03, 0x000A | (par->bgr << 12)); in set_var()
107 write_reg(par, 0x03, 0x0009 | (par->bgr << 12)); in set_var()
|
| H A D | fb_ili9320.c | 190 write_reg(par, 0x3, (par->bgr << 12) | 0x30); in set_var()
193 write_reg(par, 0x3, (par->bgr << 12) | 0x28); in set_var()
196 write_reg(par, 0x3, (par->bgr << 12) | 0x00); in set_var()
199 write_reg(par, 0x3, (par->bgr << 12) | 0x18); in set_var()
|
| H A D | fb_ili9325.c | 183 write_reg(par, 0x03, 0x0030 | (par->bgr << 12)); in set_var()
186 write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); in set_var()
189 write_reg(par, 0x03, 0x0028 | (par->bgr << 12)); in set_var()
192 write_reg(par, 0x03, 0x0018 | (par->bgr << 12)); in set_var()
|
| H A D | fb_hx8357d.c | 46 /* Set Panel - BGR, Gate direction swapped */ in init_display()
171 val |= (par->bgr ? HX8357D_MADCTL_RGB : HX8357D_MADCTL_BGR); in set_var()
|
| H A D | fb_st7789v.c | 68 #define MADCTL_BGR BIT(3) /* bitmask for RGB/BGR order */
265 * set_var() - apply LCD properties like rotation and BGR mode
275 if (par->bgr) in set_var()
|
| H A D | fb_ssd1331.c | 33 write_reg(par, 0xa0, 0x60 | (par->bgr << 2)); in init_display()
35 write_reg(par, 0xa0, 0x72 | (par->bgr << 2)); in init_display()
|
| H A D | fb_ili9163.c | 148 * 3) RGB: 1(BGR), 0(RGB) Color Space
183 if (par->bgr) in set_var()
|
| H A D | fb_ili9340.c | 114 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, val | (par->bgr << 3)); in set_var()
|
| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | am335x-boneblack-hdmi.dtsi | 56 /* If you want to get 24 bit RGB and 16 BGR mode instead of
57 * current 16 bit RGB and 24 BGR modes, set the propety
81 /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
|
| H A D | am335x-osd3358-sm-red.dts | 39 /* If you want to get 24 bit RGB and 16 BGR mode instead of
40 * current 16 bit RGB and 24 BGR modes, set the propety
65 /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
|
| /linux/Documentation/fb/ |
| H A D | efifb.rst | 53 <xres>x<yres>[-(rgb|bgr|<bpp>)]
57 "rgb" or "bgr" to match specifically those pixel formats, or a number
|
| /linux/Documentation/devicetree/bindings/display/panel/ |
| H A D | panel-mipi-dbi-spi.yaml | 56 The MIPI DCS command set_address_mode (36h) has one bit that controls RGB/BGR
57 order. This gives each supported RGB format a BGR variant.
|
| /linux/Documentation/devicetree/bindings/leds/ |
| H A D | allwinner,sun50i-a100-ledc.yaml | 61 - bgr
|
| /linux/drivers/video/fbdev/ |
| H A D | atmel_lcdfb.c | 469 /* Older SOCs use IBGR:555 rather than BGR:565. */ in atmel_lcdfb_check_var()
480 /* BGR:5X5 mode */ in atmel_lcdfb_check_var()
497 /* BGR:888 mode */ in atmel_lcdfb_check_var()
733 /* old style I+BGR:555 */ in atmel_lcdfb_setcolreg()
743 /* new style BGR:565 / RGB:565 */ in atmel_lcdfb_setcolreg()
|
| /linux/drivers/gpu/drm/tve200/ |
| H A D | tve200_drm.h | 95 #define TVE200_BGR BIT(1) /* 0 = RGB, 1 = BGR */
|
| /linux/drivers/gpu/drm/pl111/ |
| H A D | pl111_drm.h | 109 * BGR/RGB routing
|
| /linux/include/video/ |
| H A D | atmel_lcdc.h | 15 * Some Atmel chips use BGR color mode (instead of standard RGB)
|