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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfbfmin.td21 : SDTypeProfile<1, 1, [SDTCisVT<0, bf16>, SDTCisVT<1, f32>]>;
23 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, bf16>]>;
35 def FCVT_BF16_S : FPUnaryOp_r_frm<0b0100010, 0b01000, FPR16, FPR32, "fcvt.bf16.s">,
37 def FCVT_S_BF16 : FPUnaryOp_r_frm<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16">,
47 def : LdPat<load, FLH, bf16>;
50 def : StPat<store, FSH, FPR16, bf16>;
53 // f32 -> bf16, bf16 -> f32
54 def : Pat<(bf16 (riscv_fpround_bf16 FPR32:$rs1)),
56 def : Pat<(riscv_fpextend_bf16 (bf16 FPR1
[all...]
H A DRISCVFeatures.td321 : RISCVExtension<"zfbfmin", 1, 0, "'Zfbfmin' (Scalar BF16 Converts)",
325 "'Zfbfmin' (Scalar BF16 Converts)">;
333 "'Zfbfmin' (Scalar BF16 Converts)">;
698 : RISCVExtension<"zvfbfmin", 1, 0, "'Zvbfmin' (Vector BF16 Converts)",
702 "'Zvfbfmin' (Vector BF16 Converts)">;
706 "'Zvfbfwma' (Vector BF16 widening mul-add)",
710 "'Zvfbfwma' (Vector BF16 widening mul-add)">;
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.td74 def bf16 : VTFP<16, 10>; // 16-bit brain floating point value
173 def v2bf16 : VTVec<2, bf16, 99>; // 2 x bf16 vector value
174 def v3bf16 : VTVec<3, bf16, 100>; // 3 x bf16 vector value
175 def v4bf16 : VTVec<4, bf16, 101>; // 4 x bf16 vector value
176 def v8bf16 : VTVec<8, bf16, 102>; // 8 x bf16 vector value
177 def v16bf16 : VTVec<16, bf16, 103>; // 16 x bf16 vector value
178 def v32bf16 : VTVec<32, bf16, 104>; // 32 x bf16 vector value
179 def v64bf16 : VTVec<64, bf16, 105>; // 64 x bf16 vector value
180 def v128bf16 : VTVec<128, bf16, 106>; // 128 x bf16 vector value
258 def nxv1bf16 : VTScalableVec<1, bf16, 175>; // n x 1 x bf16 vector value
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FMV.td41 def : FMVExtension<"bf16", "FEAT_BF16", "+bf16", 280>;
49 def : FMVExtension<"ebf16", "FEAT_EBF16", "+bf16", 290>;
83 def : FMVExtension<"sme", "FEAT_SME", "+sme,+bf16", 430>;
84 def : FMVExtension<"sme-f64f64", "FEAT_SME_F64", "+sme,+sme-f64f64,+bf16", 560>;
85 def : FMVExtension<"sme-i16i64", "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>;
86 def : FMVExtension<"sme2", "FEAT_SME2", "+sme2,+sme,+bf16", 580>;
90 def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320>;
91 def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>;
H A DAArch64CallingConvention.td102 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,
111 CCIfType<[i1, i8, i16, f16, bf16], CCAssignToStack<8, 8>>,
148 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,
170 CCIfType<[f16, bf16], CCBitConvertToType<i16>>,
181 CCIfType<[f16, bf16], CCBitConvertToType<i16>>,
391 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,
401 CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16",
426 CCIfType<[f16, bf16, f32], CCPromoteToType<f64>>,
446 CCIfType<[f16, bf16], CCPromoteToType<f32>>,
H A DAArch64InstrInfo.td271 AssemblerPredicateWithAll<(all_of FeatureBF16), "bf16">;
1398 // Round FP32 to BF16.
1399 def : Pat<(bf16 (any_fpround (f32 FPR32:$Rn))), (BFCVT $Rn)>;
3477 // bf16 load pattern
3478 def : Pat <(bf16 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
3710 // bf16 load pattern
3711 def : Pat <(bf16 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
3926 defm : LoadInsertZeroPatterns<load, v8bf16, v4bf16, nxv8bf16, bf16, LDRHui, LDURHi,
4210 // bf16 store pattern
4211 def : Pat<(store (bf16 FPR16Op:$Rt),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td25 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
32 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
39 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
46 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
71 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
81 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
114 CCIfType<[f32, f16, v2f16, bf16, v2bf16] , CCAssignToReg<[
193 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
197 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<[
202 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
[all …]
H A DSIRegisterInfo.td379 def M0_CLASS_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, (add M0_LO16)> {
388 def SGPR_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16,
396 def SGPR_HI16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16,
405 def SGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,
461 def TTMP_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16,
587 def Reg16Types : RegisterTypes<[i16, f16, bf16]>;
689 def AGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,
741 def Pseudo_SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,
766 def SReg_32_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, …
775 def SReg_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16,
[all …]
H A DVOP3PInstructions.td1018 // For f16 and bf16 matrices A and B, each element can be modified by
1021 // neg_lo = 1 (i4 and i8) signed(sext). For f16, bf16 and f32 matrix C each
1027 // wmma f32_bf16 | neg A/B (f16 or bf16) | neg_hi = 1 abs C(f32)
1029 // wmma f16_f16 | both neg_lo,neg_hi = 1 | neg_lo = 1 neg C(f16 or bf16)
1030 // wmma bf16_bf16 | neg A/B (f16 or bf16) | neg_hi = 1 abs C(f16 or bf16)
1039 // swmmac f32_bf16 | neg A/B (f16 or bf16) | A Index - matrix C is in dst
1042 // swmmac bf16_bf16 | neg A/B (f16 or bf16) | A Index - matrix C is in dst
1052 // fp8bf8 wmmas don't use src (0 and 1) modifiers, iu use neg_lo, f16 and bf16
1054 // remaining wmmas(f16, bf16 and f8bf8) use neg_lo and neg_hi for C (C is f32
1055 // f16 or bf16). swmmac use index_key and don't use src 2 modifiers.
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Davxneconvertintrin.h28 /// Convert scalar BF16 (16-bit) floating-point element
61 /// Convert scalar BF16 (16-bit) floating-point element
160 /// Convert packed BF16 (16-bit) floating-point even-indexed elements
175 /// BF16 (16-bit) floating-point values.
193 /// Convert packed BF16 (16-bit) floating-point even-indexed elements
208 /// BF16 (16-bit) floating-point values.
292 /// Convert packed BF16 (16-bit) floating-point odd-indexed elements
307 /// BF16 (16-bit) floating-point values.
325 /// Convert packed BF16 (16-bit) floating-point odd-indexed elements
340 /// BF16 (16-bit) floating-point values.
[all …]
H A Damxintrin.h24 __attribute__((__always_inline__, __nodebug__, __target__("amx-bf16")))
213 /// Compute dot-product of BF16 (16-bit) floating-point pairs in tiles src0 and
474 /// Compute dot-product of BF16 (16-bit) floating-point pairs in tiles src0 and
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsAArch64NeonSVEBridge.def13 TARGET_BUILTIN(__builtin_sve_svget_neonq_bf16, "V8yq8y", "n", "sve,bf16")
25 TARGET_BUILTIN(__builtin_sve_svset_neonq_bf16, "q8yq8yV8y", "n", "sve,bf16")
37 TARGET_BUILTIN(__builtin_sve_svdup_neonq_bf16, "q8yV8y", "n", "sve,bf16")
H A Darm_bf16.td1 //===--- arm_bf16.td - ARM BF16 compiler interface ------------------------===//
9 // This file defines the TableGen definitions from which the ARM BF16 header
H A Darm_sve.td30 let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
142 let SVETargetGuard = "sve,bf16", SMETargetGuard = InvalidMode in {
244 let SVETargetGuard = "sve,bf16", SMETargetGuard = InvalidMode in {
255 let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
263 let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
269 let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
288 let SVETargetGuard = "sve,f64mm,bf16", SMETargetGuard = InvalidMode in {
292 let SVETargetGuard = "sve,bf16", SMETargetGuard = InvalidMode in {
296 let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
306 } // let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16"
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td17 def bf16imm : Operand<bf16>;
195 !eq(name, "bf16"): Int16Regs,
342 !strconcat(OpcStr, ".ftz.bf16 \t$dst, $a, $b;"),
343 [(set Int16Regs:$dst, (OpNode (bf16 Int16Regs:$a), (bf16 Int16Regs:$b)))]>,
348 !strconcat(OpcStr, ".bf16 \t$dst, $a, $b;"),
349 [(set Int16Regs:$dst, (OpNode (bf16 Int16Regs:$a), (bf16 Int16Regs:$b)))]>,
441 !strconcat(OpcStr, ".ftz.bf16 \t$dst, $a, $b;"),
442 [(set Int16Regs:$dst, (OpNode (bf16 Int16Regs:$a), (bf16 Int16Regs:$b)))]>,
447 !strconcat(OpcStr, ".bf16 \t$dst, $a, $b;"),
448 [(set Int16Regs:$dst, (OpNode (bf16 Int16Regs:$a), (bf16 Int16Regs:$b)))]>,
[all …]
H A DNVPTXISelLowering.cpp158 return (VT.SimpleTy == MVT::f16 || VT.SimpleTy == MVT::bf16 || in Is16bitsType()
217 case MVT::bf16: in ComputePTXValueVTs()
489 addRegisterClass(MVT::bf16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
512 setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote); in NVPTXTargetLowering()
513 if (getOperationAction(ISD::SETCC, MVT::bf16) == Promote) in NVPTXTargetLowering()
514 AddPromotedToType(ISD::SETCC, MVT::bf16, MVT::f32); in NVPTXTargetLowering()
547 for (MVT VT : {MVT::bf16, MVT::f16, MVT::v2bf16, MVT::v2f16, MVT::f32, in NVPTXTargetLowering()
604 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::bf16, Expand); in NVPTXTargetLowering()
605 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::bf16, Expand); in NVPTXTargetLowering()
625 setTruncStoreAction(MVT::f32, MVT::bf16, Expand); in NVPTXTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp173 case MVT::bf16: return "bf16"; in getEVTString()
241 case Type::BFloatTyID: return MVT(MVT::bf16); in getVT()
H A DTargetLoweringBase.cpp145 } else if (OpVT == MVT::bf16) { in getFPEXT()
167 } else if (RetVT == MVT::bf16) { in getFPROUND()
823 {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128}, in initActions()
1366 // Decide how to handle bf16. If the target does not have native bf16 support, in computeRegisterProperties()
1367 // promote it to f32, because there are no bf16 library calls (except for in computeRegisterProperties()
1368 // converting from f32 to bf16). in computeRegisterProperties()
1369 if (!isTypeLegal(MVT::bf16)) { in computeRegisterProperties()
1370 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32]; in computeRegisterProperties()
1371 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32]; in computeRegisterProperties()
1372 TransformToType[MVT::bf16] = MVT::f32; in computeRegisterProperties()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td142 CCIfType<[f16, bf16, f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
179 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_Custom_f16">>,
197 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_Custom_f16">>,
229 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_VFP_Custom_f16">>,
249 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_VFP_Custom_f16">>,
/freebsd/lib/clang/headers/
H A DMakefile250 .for hdr in bf16/bf16 cde/cde-header fp16/fp16 mve/mve-header neon/neon \
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp77 MCInstBuilder(MI.getOpcode() == CSKY::JBT_E ? CSKY::BF16 : CSKY::BT16) in expandJBTF()
186 TmpInst = MCInstBuilder(CSKY::BF16) in encodeInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td210 def BF16 : J16_B<3, "bf16">;
493 (BF16 (inst mGPR:$rs1, imm_ty:$rs2), bb:$offset)>;
503 (BF16 (CMPNE16 sGPR:$rs1, sGPR:$rs2), bb:$offset)>;
514 defm : BTF16Pat1<setult, setugt, CMPHS16, BF16>;
516 defm : BTF16Pat1<setge, setle, CMPLT16, BF16>;
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DARMTargetParser.def238 ARM_ARCH_EXT_NAME("bf16", ARM::AEK_BF16, "+bf16", "-bf16")
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml348 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
550 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
556 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp921 .Case("bf16", Intrinsic::nvvm_abs_bf16) in shouldUpgradeNVPTXBF16Intrinsic()
927 .Case("bf16", Intrinsic::nvvm_fma_rn_bf16) in shouldUpgradeNVPTXBF16Intrinsic()
929 .Case("ftz.bf16", Intrinsic::nvvm_fma_rn_ftz_bf16) in shouldUpgradeNVPTXBF16Intrinsic()
931 .Case("ftz.relu.bf16", Intrinsic::nvvm_fma_rn_ftz_relu_bf16) in shouldUpgradeNVPTXBF16Intrinsic()
933 .Case("ftz.sat.bf16", Intrinsic::nvvm_fma_rn_ftz_sat_bf16) in shouldUpgradeNVPTXBF16Intrinsic()
935 .Case("relu.bf16", Intrinsic::nvvm_fma_rn_relu_bf16) in shouldUpgradeNVPTXBF16Intrinsic()
937 .Case("sat.bf16", Intrinsic::nvvm_fma_rn_sat_bf16) in shouldUpgradeNVPTXBF16Intrinsic()
943 .Case("bf16", Intrinsic::nvvm_fmax_bf16) in shouldUpgradeNVPTXBF16Intrinsic()
945 .Case("ftz.bf16", Intrinsic::nvvm_fmax_ftz_bf16) in shouldUpgradeNVPTXBF16Intrinsic()
947 .Case("ftz.nan.bf16", Intrinsic::nvvm_fmax_ftz_nan_bf16) in shouldUpgradeNVPTXBF16Intrinsic()
[all …]

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