| /linux/Documentation/arch/powerpc/ |
| H A D | pci_iov_resource_on_powernv.rst | 107 scheme where individual function BARs can be "grouped" to fit in one or
127 for large BARs in 64-bit space:
156 PE" mode to overlay over specific BARs to work around some of that, for
157 example for devices with very large BARs, e.g., GPUs. It would make
170 PCI devices, but the BARs in VF config space headers are unusual. For
171 a non-VF device, software uses BARs in the config space header to
174 discover sizes and assign addresses. The BARs in the VF's config space
178 base address for all the corresponding VF(n) BARs. For example, if the
190 window with 1MB segments. VF BARs that are 1MB or larger could be
193 flexible, but it works best when all the VF BARs are the same size. If
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| /linux/drivers/accel/habanalabs/common/pci/ |
| H A D | pci.c | 23 * hl_pci_bars_map() - Map PCI BARs.
45 bar = i * 2; /* 64-bit BARs */ in hl_pci_bars_map()
61 bar = i * 2; /* 64-bit BARs */ in hl_pci_bars_map()
72 * hl_pci_bars_unmap() - Unmap PCI BARS.
75 * Release all PCI BARs and unmap their virtual addresses.
83 bar = i * 2; /* 64-bit BARs */ in hl_pci_bars_unmap()
374 * Set DMA masks, initialize the PCI controller and map the PCI BARs.
432 * Unmap PCI bars and disable PCI device.
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| /linux/drivers/scsi/csiostor/ |
| H A D | csio_init.c | 184 * @bars: Bitmask of bars to be requested.
190 csio_pci_init(struct pci_dev *pdev, int *bars) in csio_pci_init() argument
194 *bars = pci_select_bars(pdev, IORESOURCE_MEM); in csio_pci_init()
199 if (pci_request_selected_regions(pdev, *bars, KBUILD_MODNAME)) in csio_pci_init()
217 pci_release_selected_regions(pdev, *bars); in csio_pci_init()
228 * @bars: Bars to be released.
232 csio_pci_exit(struct pci_dev *pdev, int *bars) in csio_pci_exit() argument
234 pci_release_selected_regions(pdev, *bars); in csio_pci_exit()
512 * Allocates HW structure, DMA, memory resources, maps BARS to
930 * - Allocates HW structure, DMA, memory resources, maps BARS to
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| /linux/arch/s390/pci/ |
| H A D | pci.c | 296 idx = zdev->bars[bar].map_idx; in pci_iomap_range_fh()
315 iova = ioremap((unsigned long) zdev->bars[bar].mio_wt, barsize); in pci_iomap_range_mio()
345 iova = ioremap((unsigned long) zdev->bars[bar].mio_wb, barsize); in pci_iomap_wc_range_mio()
430 (resource_size_t __force) zdev->bars[i].mio_wt; in zpci_map_resources()
487 if (!zdev->bars[bar].size) in zpci_do_update_iomap_fh()
489 idx = zdev->bars[bar].map_idx; in zpci_do_update_iomap_fh()
540 if (!zdev->bars[i].size) in zpci_setup_bus_resources()
545 zdev->bars[i].map_idx = entry; in zpci_setup_bus_resources()
549 if (zdev->bars[i].val & 8) in zpci_setup_bus_resources()
551 if (zdev->bars[i].val & 4) in zpci_setup_bus_resources()
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| H A D | pci_clp.c | 160 zdev->bars[i].val = le32_to_cpu(response->bar[i]); in clp_store_query_pci_fn()
161 zdev->bars[i].size = response->bar_size[i]; in clp_store_query_pci_fn()
192 zdev->bars[i].mio_wb = (void __iomem *) response->mio.addr[i].wb; in clp_store_query_pci_fn()
193 zdev->bars[i].mio_wt = (void __iomem *) response->mio.addr[i].wt; in clp_store_query_pci_fn()
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| /linux/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| H A D | nfp6000_pcie.c | 10 * Multiplexes the NFP BARs between NFP internal resources and
13 * The BARs are managed with refcounts and are allocated/acquired
106 /* The number of explicit BARs to reserve.
149 int bars; member
347 /* We don't match explicit bars through the area interface */ in matching_bar()
372 for (n = 0; n < nfp->bars; n++) { in find_matching_bar()
390 for (n = 0; n < nfp->bars; n++) { in find_unused_bar_noblock()
519 /* Map all PCI bars and fetch the actual BAR configurations from the
566 snprintf(status_msg, sizeof(status_msg) - 1, "RESERVED BARs: "); in enable_bars()
575 /* Skip over BARs that are not IORESOURCE_MEM */ in enable_bars()
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| /linux/arch/powerpc/platforms/powernv/ |
| H A D | pci-sriov.c | 21 * For conventional PCI devices this isn't really an issue since PCI device BARs
29 * allocate the SR-IOV BARs in a way that lets us map them using the MBT.
45 * (num-vfs * num-sriov-bars) in total. To use a) we need the size of each segment
56 * At this point the device has been probed and the device's BARs are sized,
57 * but no resource allocations have been done. The SR-IOV BARs are sized
63 * sorts the BARs on a bus by their required alignment, which is calculated
109 * it only usable for devices with very large per-VF BARs. Such devices are
123 * us to support SR-IOV BARs in the 32bit MMIO window. This is useful since
215 /* Save ourselves some MMIO space by disabling the unusable BARs */ in pnv_pci_ioda_fixup_iov_resources()
258 * BARs would not be placed in the correct PE. in pnv_pci_iov_resource_alignment()
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| /linux/drivers/ntb/hw/idt/ |
| H A D | Kconfig | 18 and SWPORTxCTL registers). Then all NT-function BARs must be enabled
19 with chosen valid aperture. For memory windows related BARs the
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| H A D | ntb_hw_idt.h | 972 * @IDT_BAR_CNT: Number of BARs of each port
1184 * @bars: BARs related registers
1188 struct idt_ntb_bar bars[IDT_BAR_CNT]; member
1201 * @bars: BARs related registers
1211 struct idt_ntb_bar bars[IDT_BAR_CNT]; member
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| /linux/Documentation/PCI/endpoint/ |
| H A D | pci-ntb-function.rst | 12 machine, expose memory ranges as BARs, and perform DMA. They also support
230 one is permitted. All these regions should be mapped to BARs for hosts to
248 be enough BARs for all the regions in a platform that supports only 64-bit
249 BARs.
252 packed and mapped to BARs in a way that provides NTB functionality and
269 With this scheme, for the basic NTB functionality 3 BARs should be sufficient.
339 space. Allocating and configuring BARs for doorbell and memory window1
348 is mapped to separate BARs.
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| H A D | pci-vntb-function.rst | 103 32-bit BARs.
116 64-bit BARs.
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| /linux/drivers/pci/ |
| H A D | setup-res.c | 35 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ in pci_std_update_resource()
40 * Ignore resources for unimplemented BARs and unused resource slots in pci_std_update_resource()
41 * for 64 bit BARs. in pci_std_update_resource()
75 * Apparently some Matrox devices have ROM BARs that read in pci_std_update_resource()
76 * as zero when disabled, so don't update ROM BARs unless in pci_std_update_resource()
80 * disabled ROM can conflict with other BARs. in pci_std_update_resource()
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| H A D | pci.c | 776 * Goes over standard PCI resources (BARs) and checks if the given resource
1055 * @dev: PCI device to have its BARs restored
1297 * restore the device's BARs subsequently (1 is returned in that case).
1368 * to confirm the state change, restore its BARs if they might be lost and
1404 * restore at least the BARs so that the device will be in pci_set_full_power_state()
1808 /* Restore BARs before the command register. */ in pci_restore_config_space()
1985 int __weak pcibios_enable_device(struct pci_dev *dev, int bars) in pcibios_enable_device() argument
1987 return pci_enable_resources(dev, bars); in pcibios_enable_device()
2012 static int do_pci_enable_device(struct pci_dev *dev, int bars) in do_pci_enable_device() argument
2031 err = pcibios_enable_device(dev, bars); in do_pci_enable_device()
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| H A D | devres.c | 23 * Legacy struct storing addresses to whole mapped BARs.
650 * Unmap a BAR and release its region manually. Only pass BARs that were
667 * pcim_iomap_regions - Request and iomap PCI BARs (DEPRECATED)
669 * @mask: Mask of BARs to request and iomap
858 * only ever keeps track of whole BARs. in pcim_iomap_range()
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| H A D | iov.c | 657 int bars = 0; in sriov_enable() local
680 bars |= (1 << idx); in sriov_enable()
699 if (pci_enable_resources(dev, bars)) { in sriov_enable()
700 pci_err(dev, "SR-IOV: IOV BARS not allocated\n"); in sriov_enable()
845 /* Sizing SR-IOV BARs with VF Enable cleared - no decode */ in sriov_init()
1063 * Ignore unimplemented BARs, unused resource slots for 64-bit in pci_iov_update_resource()
1064 * BARs, and non-movable resources, e.g., those described via in pci_iov_update_resource()
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| /linux/drivers/vdpa/solidrun/ |
| H A D | snet_vdpa.h | 143 /* PCI BARs */
144 void __iomem *bars[PCI_STD_NUM_BARS]; member
170 return ioread32(psnet->bars[psnet->barno] + off); in psnet_read32()
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| /linux/arch/sparc/kernel/ |
| H A D | leon_pci_grpci2.c | 31 * - barcfgs : Custom Configuration of Host's 6 target BARs
79 unsigned int bars[6]; /* 0x20 read-only PCI BARs */ member
605 /* Setup the Host's PCI Target BARs for other peripherals to access, in grpci2_hw_init()
606 * and do DMA to the host's memory. The target BARs can be sized and in grpci2_hw_init()
609 * User may set custom target BARs, but default is: in grpci2_hw_init()
610 * The first BARs is used to map kernel low (DMA is part of normal in grpci2_hw_init()
612 * PCI bus, the other BARs are disabled. We assume that the first BAR in grpci2_hw_init()
617 /* Target BARs must have the proper alignment */ in grpci2_hw_init()
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| /linux/Documentation/devicetree/bindings/i2c/ |
| H A D | i2c-pxa-pci-ce4100.txt | 5 PCI device has three PCI-bars, each bar contains a complete I2C
20 1:1 mapped to the BARs, and the second is the
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| /linux/drivers/pci/endpoint/functions/ |
| H A D | pci-epf-ntb.c | 223 * BAR_MW4 for rest of the BARs of epf_ntb_epc that is connected to HOST1. This
231 * mapped to a single BAR (BAR2) above for 32-bit BARs. The exact BAR that's
726 * other BARs for peer scratchpad (because of 64-bit BARs or reserved BARs).
771 * other BARs for peer scratchpad (because of 64-bit BARs or reserved BARs).
842 * the default self scratchpad BAR, an NTB could have other BARs for self
843 * scratchpad (because of reserved BARs). This function can get the exact BAR
887 * NTB could have other BARs for self scratchpad (because of reserved BARs).
1219 * Clear doorbell and memory BARs (remove inbound ATU configuration). In the above
1422 * epf_ntb_db_mw_bar_init() - Configure Doorbell and Memory window BARs
1631 * epf_ntb_init_epc_bar_interface() - Identify BARs to be used for each of
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| H A D | pci-epf-vntb.c | 332 * the default self scratchpad BAR, an NTB could have other BARs for self
333 * scratchpad (because of reserved BARs). This function can get the exact BAR
504 * epf_ntb_db_bar_init() - Configure Doorbell window BARs
566 * epf_ntb_mw_bar_init() - Configure Memory window BARs
624 * epf_ntb_mw_bar_clear() - Clear Memory window BARs
626 * @num_mws: the number of Memory window BARs that to be cleared
717 * epf_ntb_init_epc_bar() - Identify BARs to be used for each of the NTB
737 /* These are required BARs which are mandatory for NTB functionality */ in epf_ntb_init_epc_bar()
746 /* These are optional BARs which don't impact NTB functionality */ in epf_ntb_init_epc_bar()
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| /linux/drivers/gpu/drm/i915/gvt/ |
| H A D | cfg_space.c | 189 struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar; in emulate_pci_bar_write() local
202 size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1); in emulate_pci_bar_write()
213 size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1); in emulate_pci_bar_write()
219 /* Unimplemented BARs */ in emulate_pci_bar_write()
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| /linux/drivers/pci/hotplug/ |
| H A D | ibmphp_pci.c | 136 /* We need to do this in case some other BARs were properly inserted */ in ibmphp_configure_card()
149 /* We need to do this in case some other BARs were properly inserted */ in ibmphp_configure_card()
181 /* We need to do this in case some other BARs were properly inserted */ in ibmphp_configure_card()
250 /* We need to do this in case some other BARs were properly inserted */ in ibmphp_configure_card()
283 /* We need to do this in case some other BARs were properly inserted */ in ibmphp_configure_card()
325 * This function configures the pci BARs of a single device.
355 for (count = 0; address[count]; count++) { /* for 6 BARs */ in configure_device()
631 for (count = 0; address[count]; count++) { /* for 2 BARs */ in configure_bridge()
786 /* for 2 BARs */ in configure_bridge()
1025 for (i = 0; i < 2; i++) { /* for 2 BARs */ in configure_bridge()
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| /linux/include/linux/ |
| H A D | 8250_pci.h | 13 /* Use successive BARs (PCI base address registers),
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| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | Kconfig | 38 GPUs with large memory BARs that expose the entire VRAM in PCIe bus
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| /linux/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_sriov.h | 60 /* bars */
67 struct bnx2x_vf_bar bars[PCI_SRIOV_NUM_BARS]; member
192 /* bars */
193 struct bnx2x_vf_bar bars[PCI_SRIOV_NUM_BARS]; member
|