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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie.c261 al_reg_write32(regs->axi.parity.en_axi, in al_pcie_port_axi_parity_int_config()
265 al_reg_write32_masked(regs->axi.ctrl.global, in al_pcie_port_axi_parity_int_config()
277 al_reg_write32_masked(regs->axi.ctrl.global, in al_pcie_port_axi_parity_int_config()
290 al_reg_write32_masked(&regs->axi.int_grp_a->mask, in al_pcie_port_axi_parity_int_config()
330 regs->axi.ordering.pos_cntl, in al_pcie_port_relaxed_pcie_ordering_config()
366 dev_id = al_reg_read32(&regs->axi.device_id.device_rev_id) & in al_pcie_rev_id_get()
603 al_reg_write32(regs->axi.conf.zero_lane0, reg); in al_pcie_port_gen3_params_config()
604 al_reg_write32(regs->axi.conf.zero_lane1, reg); in al_pcie_port_gen3_params_config()
605 al_reg_write32(regs->axi.conf.zero_lane2, reg); in al_pcie_port_gen3_params_config()
606 al_reg_write32(regs->axi.conf.zero_lane3, reg); in al_pcie_port_gen3_params_config()
[all …]
H A Dal_hal_udma_regs_s2m.h77 /* [0x24] AXI outstanding read configuration */
79 /* [0x28] AXI outstanding write configuration */
131 /* [0x30] S2M AXI data FIFO status */
309 /* AXI write ID (AWID) */
327 * AXI Master QoS.
328 * Used for arbitration between AXI masters
337 /* AXI read ID (ARID) */
355 * AXI Master QoS.
356 * Used for arbitration between AXI masters
365 /* AXI write ID (AWID) */
[all …]
H A Dal_hal_udma_regs_m2s.h77 /* [0x24] AXI outstanding configuration */
365 /* AXI write ID (AWID) */
383 * AXI Master QoS.
384 * Used for arbitration between AXI masters
393 /* AXI read ID (ARID) */
411 * AXI Master QoS.
412 * Used for arbitration between AXI masters
421 /* AXI read ID (ARID) */
439 * AXI Master QoS
440 * Used for arbitration between AXI masters
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie.yaml272 - const: axi # AXI reset
297 - const: master_bus # Master AXI clock
298 - const: slave_bus # Slave AXI clock
320 - const: master_bus # Master AXI clock
321 - const: slave_bus # Slave AXI clock
327 - const: axi_m # AXI master reset
328 - const: axi_s # AXI slave reset
334 - const: axi_m_sticky # AXI sticky reset
356 - const: bus_master # Master AXI cloc
[all...]
H A Dqcom,pcie.txt107 - "bus_master" Master AXI clock
108 - "bus_slave" Slave AXI clock
117 - "bus_master" Master AXI clock
118 - "bus_slave" Slave AXI clock
125 - "axi_m" AXI Master clock
126 - "axi_s" AXI Slave clock
135 - "axi_m" AXI Master clock
136 - "axi_s" AXI Slave clock
137 - "axi_bridge" AXI bridge clock
146 - "master_bus" AXI Master clock
[all …]
H A Dxilinx-pcie.txt1 * Xilinx AXI PCIe Root Port Bridge DT description
8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9 - reg: Should contain AXI PCIe registers location and length
11 - interrupts: Should contain AXI PCIe interrupt
42 pci_express: axi-pcie@50000000 {
46 compatible = "xlnx,axi-pcie-host-1.00.a";
66 pci_express: axi-pcie@10000000 {
70 compatible = "xlnx,axi-pcie-host-1.00.a";
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dsnps,dw-axi-dmac.yaml4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
7 title: Synopsys DesignWare AXI DMA Controller
13 Synopsys DesignWare AXI DMA Controller DT Binding
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
23 - starfive,jh7110-axi-dma
67 Number of AXI masters supported by the hardware.
73 AXI data width supported by hardware.
92 snps,axi-max-burst-len:
94 Restrict master AXI burst length by value specified in this property.
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H A Dsnps,dw-axi-dmac.txt1 Synopsys DesignWare AXI DMA Controller
4 - compatible: "snps,axi-dma-1.01a"
9 - snps,dma-masters: Number of AXI masters supported by the hardware.
10 - snps,data-width: Maximum AXI data width supported by hardware.
19 - snps,axi-max-burst-len: Restrict master AXI burst length by value specified
20 in this property. If this property is missing the maximum AXI burst length
26 compatible = "snps,axi-dma-1.01a";
38 snps,axi-max-burst-len = <16>;
H A Dadi,axi-dmac.txt1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
7 - clocks: Phandle and specifier to the controllers AXI interface clock
26 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
27 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
36 DMA clients connected to the AXI-DMAC DMA controller must use the format
43 compatible = "adi,axi-dmac-1.00.a";
/freebsd/sys/contrib/device-tree/Bindings/dma/xilinx/
H A Dxilinx_dma.txt1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
47 Optional properties for AXI DMA and MCDMA:
53 Optional properties for AXI DM
[all...]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dallwinner,sun4i-a10-axi-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml#
7 title: Allwinner A10 AXI Clock
21 - allwinner,sun4i-a10-axi-clk
22 - allwinner,sun8i-a23-axi-clk
44 axi@1c20054 {
46 compatible = "allwinner,sun4i-a10-axi-clk";
49 clock-output-names = "axi";
55 compatible = "allwinner,sun8i-a23-axi-clk";
58 clock-output-names = "axi";
H A Dbaikal,bt1-ccu-div.yaml26 3) AXI-bus clock dividers (AXI) - described in this binding file.
38 +----+ | | | +-|AXI|-|- AXI-bus
52 domain (like AXI-bus or System Device consumers). The dividers have the
78 Similarly the dividers with output clocks utilized as AXI-bus reference clocks
79 are called AXI-bus CCU. Both of them use the common clock bindings with no
82 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
90 const: baikal,bt1-ccu-axi
125 - baikal,bt1-ccu-axi
150 # AXI-bus Clock Control Unit node:
155 compatible = "baikal,bt1-ccu-axi";
H A Daxi-clkgen.txt1 Binding for the axi-clkgen clock generator
8 - compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
10 - reg : Address and length of the axi-clkgen register set.
21 compatible = "adi,axi-clkgen";
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dxlnx,axi-ethernet.yaml4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi
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H A Dxilinx_axienet.txt1 XILINX AXI ETHERNET Device Tree Bindings
4 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
10 Management configuration is done through the AXI interface, while payload is
11 sent and received through means of an AXI DMA controller. This driver
12 includes the DMA driver code, so this driver is incompatible with AXI DMA
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
21 and length of the AXI DMA controller IO space, unless
47 s_axi_lite_clk: Clock for AXI register slave interface
64 for the AXI DMA controller used by this device.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Dxilinx-pr-decoupler.txt10 Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager
13 The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic
17 that can occur if AXI transactions are interrupted by DFX
26 "xlnx,dfx-axi-shutdown-manager-1.00" followed by
27 "xlnx,dfx-axi-shutdown-manager"
46 Dynamic Function eXchange AXI shutdown manager:
48 compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
49 "xlnx,dfx-axi-shutdown-manager";
H A Dxlnx,pr-decoupler.yaml7 title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
21 Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager Softcore
23 eXchange AXI shutdown manager prevents AXI traffic from passing through the
26 preventing the system deadlock that can occur if AXI transactions are
38 - const: xlnx,dfx-axi-shutdown-manager-1.00
39 - const: xlnx,dfx-axi-shutdown-manager
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dbaikal,bt1-axi.yaml5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
8 title: Baikal-T1 AXI-bus
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
21 an IRQ is raised and a faulty situation is reported to the AXI EHB
22 (Errors Handler Block) embedded on top of the DW AXI Interconnect and
31 const: baikal,bt1-axi
36 - description: Synopsys DesignWare AXI Interconnect QoS registers
37 - description: AXI EHB MMIO system controller registers
87 compatible = "baikal,bt1-axi", "simple-bus";
H A Dbrcm,bus-axi.txt1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
9 The cores on the AXI bus are automatically detected by bcma with the
17 The top-level axi bus may contain children representing attached cores
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dxilinx_can.txt1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
16 - "can_clk", "s_axi_aclk" (For AXI CAN and CAN FD).
19 - tx-fifo-depth : Can Tx fifo depth (Zynq, Axi CAN).
20 - rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in
40 For Axi CAN Dts file:
41 axi_can_0: axi-can@40000000 {
42 compatible = "xlnx,axi-can-1.00.a";
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dadi,axi-spdif-tx.txt1 ADI AXI-SPDIF controller
4 - compatible : Must be "adi,axi-spdif-tx-1.00.a"
7 The controller expects two clocks, the clock used for the AXI interface and
9 - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
24 compatible = "adi,axi-spdif-tx-1.00.a";
27 clock-names = "axi", "ref";
H A Dadi,axi-i2s.txt1 ADI AXI-I2S controller
7 - compatible : Must be "adi,axi-i2s-1.00.a"
10 The controller expects two clocks, the clock used for the AXI interface and
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
28 compatible = "adi,axi-i2s-1.00.a";
31 clock-names = "axi", "ref";
/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Dadi,axi-fan-control.yaml5 $id: http://devicetree.org/schemas/hwmon/adi,axi-fan-control.yaml#
8 title: Analog Devices AXI FAN Control
14 Bindings for the Analog Devices AXI FAN Control driver. Specifications of the
22 - adi,axi-fan-control-1.00.a
51 fpga_axi: fpga-axi {
55 axi_fan_control: axi-fan-control@80000000 {
56 compatible = "adi,axi-fan-control-1.00.a";
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dadi,axi-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
7 title: Analog Devices AXI ADC IP core
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
26 - adi,axi-adc-10.0.a
53 axi-adc@44a00000 {
54 compatible = "adi,axi-adc-10.0.a";
H A Dxilinx-xadc.txt10 on all series 7 platforms and is a softmacro with a AXI interface. This binding
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
33 when using the axi-xadc or the axi-system-management-wizard this must be
34 the clock that provides the clock to the AXI bus interface of the core.
110 compatible = "xlnx,axi-xadc-1.00.a";

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