Lines Matching full:axi

77 	/* [0x24] AXI outstanding read configuration */
79 	/* [0x28] AXI outstanding write configuration */
131 	/* [0x30] S2M AXI data FIFO status */
309 /* AXI write  ID (AWID) */
327  * AXI Master QoS.
328  * Used for arbitration between AXI masters
337 /* AXI read  ID (ARID) */
355  * AXI Master QoS.
356  * Used for arbitration between AXI masters
365 /* AXI write  ID (AWID) */
383  * AXI Master QoS.
384  * Used for arbitration between AXI masters
394  * Defines the maximum number of AXI beats for a single AXI burst. This value is
402  * Defines the maximum number of AXI beats for a single AXI burst. This value is
415  * Defines the maximum number of AXI beats for a single AXI burst. This value is
422  * (AXI beats).
431  * Maximum number of outstanding descriptor reads to the AXI.
432  * (AXI transactions).
442  * Maximum number of outstanding data writes to the AXI.
443  * (AXI transactions).
448  * Maximum number of outstanding data beats for data write to AXI.
449  * (AXI beats).
454  * Maximum number of outstanding descriptor writes to the AXI.
455  * (AXI transactions).
460  * Maximum number of outstanding data beats for descriptor write to AXI.
461  * (AXI beats).
685  * 1 - Data write is always in Full AXI bus width (128 bit)
773 /* Maximum number of outstanding data writes to the AXI */
777  * Maximum number of outstanding data beats for data write to AXI.
778  * (AXI beats)
783  * Maximum number of outstanding descriptor reads to the AXI.
784  * (AXI transactions)
789  * Maximum number of outstanding data beats for descriptor write to AXI.
790  * (AXI beats)
796 /* Maximum number of outstanding descriptor reads to the AXI */
805  * Configure the AXI AWCACHE
811  * Configure the AXI AWCACHE
826  * Configure the AXI AWCACHE
832  * AXI QoS
833  * This value is used in AXI transactions associated with this queue and the