Home
last modified time | relevance | path

Searched full:andes (Results 1 – 25 of 36) sorted by relevance

12

/linux/arch/riscv/
H A DKconfig.errata4 bool "Andes AX45MP errata"
7 All Andes errata Kconfig depend on this Kconfig. Disabling
8 this Kconfig will disable all Andes errata. Please say "Y"
9 here if your platform uses Andes CPU cores.
14 bool "Apply Andes cache management errata"
20 non-standard handling on non-coherent operations on Andes cores.
H A DKconfig.vendor6 menu "Andes" menu
8 bool "Andes vendor extension support"
12 Say N here if you want to disable all Andes vendor extension
13 support. This will cause any Andes vendor extensions that are
H A DKconfig.socs4 bool "Andes SoCs"
8 This enables support for Andes SoC platform hardware.
/linux/include/linux/soc/andes/
H A Dirq.h3 * Copyright (C) 2023 Andes Technology Corporation
8 /* Andes PMU irq number */
13 /* Andes PMU related registers */
/linux/Documentation/devicetree/bindings/riscv/
H A Dandes.yaml4 $id: http://devicetree.org/schemas/riscv/andes.yaml#
7 title: Andes SoC-based boards
13 Andes SoC-based boards
/linux/arch/riscv/kernel/vendor_extensions/
H A Dandes.c5 #include <asm/vendor_extensions/andes.h>
10 /* All Andes vendor extensions supported in Linux */
H A DMakefile3 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o
/linux/drivers/cache/
H A DKconfig14 bool "Andes Technology AX45MP L2 Cache controller"
17 Support for the L2 cache controller on Andes Technology AX45MP platforms.
H A Dax45mp_cache.c3 * non-coherent cache functions for Andes AX45MP
194 * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size in ax45mp_cache_init()
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dandestech,plicsw.yaml7 title: Andes machine-level software interrupt controller
10 In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
/linux/Documentation/devicetree/bindings/timer/
H A Dandestech,plmt0.yaml7 title: Andes machine-level timer
10 The Andes machine-level timer device (PLMT0) provides machine-level timer
/linux/drivers/irqchip/
H A Dirq-riscv-intc.c20 #include <linux/soc/andes/irq.h>
71 * Andes specific S-mode local interrupt causes (hwirq) in andes_intc_irq_mask()
250 IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
/linux/arch/riscv/include/asm/
H A Dvermagic.h2 /* Copyright (C) 2017 Andes Technology Corporation */
H A Dmodule.lds.h2 /* Copyright (C) 2017 Andes Technology Corporation */
H A Dkasan.h2 /* Copyright (C) 2019 Andes Technology Corporation */
/linux/drivers/rtc/
H A Drtc-atcrtc100.c3 * Driver for Andes ATCRTC100 real time clock.
5 * Copyright (C) 2025 Andes Technology Corporation
380 MODULE_DESCRIPTION("Andes ATCRTC100 driver");
/linux/arch/riscv/boot/dts/
H A DMakefile3 subdir-y += andes
/linux/arch/riscv/boot/dts/andes/
H A Dqilai-voyager.dts3 * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
/linux/arch/riscv/errata/
H A DMakefile15 obj-$(CONFIG_ERRATA_ANDES) += andes/
/linux/Documentation/devicetree/bindings/rtc/
H A Dandestech,atcrtc100.yaml7 title: Andes ATCRTC100 Real-Time Clock
/linux/drivers/perf/
H A DKconfig119 bool "Andes custom PMU support"
123 The Andes cores implement the PMU overflow extension very
/linux/arch/riscv/kernel/
H A Dvendor_extensions.c8 #include <asm/vendor_extensions/andes.h>
H A Dmcount.S2 /* Copyright (C) 2017 Andes Technology Corporation */
/linux/tools/perf/pmu-events/arch/riscv/
H A Dmapfile.csv26 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
/linux/include/uapi/linux/
H A Delf-em.h44 #define EM_NDS32 167 /* Andes Technology compact code size

12