Searched full:andes (Results 1 – 25 of 29) sorted by relevance
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4 bool "Andes AX45MP errata"7 All Andes errata Kconfig depend on this Kconfig. Disabling8 this Kconfig will disable all Andes errata. Please say "Y"9 here if your platform uses Andes CPU cores.14 bool "Apply Andes cache management errata"20 non-standard handling on non-coherent operations on Andes cores.
6 menu "Andes" menu8 bool "Andes vendor extension support"12 Say N here if you want to disable all Andes vendor extension13 support. This will cause any Andes vendor extensions that are
3 * Copyright (C) 2023 Andes Technology Corporation8 /* Andes PMU irq number */13 /* Andes PMU related registers */
4 $id: http://devicetree.org/schemas/riscv/andes.yaml#7 title: Andes SoC-based boards13 Andes SoC-based boards
5 bool "Andes Technology AX45MP L2 Cache controller"9 Support for the L2 cache controller on Andes Technology AX45MP platforms.
3 * non-coherent cache functions for Andes AX45MP194 * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size in ax45mp_cache_init()
5 #include <asm/vendor_extensions/andes.h>10 /* All Andes vendor extensions supported in Linux */
3 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o
7 title: Andes machine-level software interrupt controller10 In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
7 title: Andes machine-level timer10 The Andes machine-level timer device (PLMT0) provides machine-level timer
20 #include <linux/soc/andes/irq.h>71 * Andes specific S-mode local interrupt causes (hwirq) in andes_intc_irq_mask()249 IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
2 /* Copyright (C) 2017 Andes Technology Corporation */
2 /* Copyright (C) 2019 Andes Technology Corporation */
3 * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
15 obj-$(CONFIG_ERRATA_ANDES) += andes/
24 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
119 bool "Andes custom PMU support"123 The Andes cores implement the PMU overflow extension very
8 #include <asm/vendor_extensions/andes.h>
44 #define EM_NDS32 167 /* Andes Technology compact code size