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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCVXAndes.td1 //===- IntrinsicsRISCVXAndes.td - Andes intrinsics ---------*- tablegen -*-===//
9 // This file defines all of the Andes vendor intrinsics for RISC-V.
14 // Andes Vector BFloat16 Conversion Extension
18 // Andes Vector INT4 Load Extension
22 // Andes Vector Packed FP16 Extension
26 // Andes Vector Dot Product Extension
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_andes_vector.td1 //==--- riscv_andes_vector.td - RISC-V Andes Builtin function list --------===//
9 // This file defines the builtins for RISC-V Andes Vector Extension. See:
11 // https://github.com/andestech/andes-vector-intrinsic-doc
21 // Andes Vector BFLOAT16 Conversion Extension (XAndesVBFHCvt)
67 // Andes Vector INT4 Load Extension (XAndesVSIntLoad)
96 // Andes Vector Packed FP16 Extension (XAndesVPackFPH)
160 // Andes Vector Dot Product Extension (XAndesVDot)
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dandes.yaml4 $id: http://devicetree.org/schemas/riscv/andes.yaml#
7 title: Andes SoC-based boards
13 Andes SoC-based boards
H A Dextensions.yaml657 # Andes
660 The Andes Technology performance monitor extension for counter overflow
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVProcessors.td698 def ANDES_A25 : RISCVProcessorModel<"andes-a25",
711 def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
729 def ANDES_45 : RISCVTuneProcessorModel<"andes-45-series",
732 def ANDES_N45 : RISCVProcessorModel<"andes-n45",
746 def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
760 def ANDES_A45 : RISCVProcessorModel<"andes-a45",
774 def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
788 def ANDES_AX45MPV : RISCVProcessorModel<"andes-ax45mpv",
H A DRISCVFeatures.td1596 // Andes Extension(s)
1599 : RISCVExtension<5, 0, "Andes Performance Extension">;
1603 "'XAndesPerf' (Andes Performance Extension)">;
1606 : RISCVExtension<5, 0, "Andes Scalar BFLOAT16 Conversion Extension",
1611 "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)">;
1614 : RISCVExtension<5, 0, "Andes Vector BFLOAT16 Conversion Extension",
1619 "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)">;
1622 : RISCVExtension<5, 0, "Andes Vector INT4 Load Extension",
1627 "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)">;
1631 "Andes Vector Packed FP16 Extension", [FeatureStdExtF]>;
[all …]
H A DRISCVSchedAndes45.td26 // Andes 45 series CPU
H A DRISCVInstrInfoXAndes.td9 // This file describes the vendor extensions defined by Andes Technology.
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dandestech,plicsw.yaml7 title: Andes machine-level software interrupt controller
10 In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dandestech,plmt0.yaml7 title: Andes machine-level timer
10 The Andes machine-level timer device (PLMT0) provides machine-level timer
H A Dandestech,atcpit100-timer.txt3 ATCPIT100 is a generic IP block from Andes Technology, embedded in
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ELFRelocs/
H A DRISCV_nonstandard.def30 // Andes Nonstandard Relocations
32 ELF_RISCV_NONSTANDARD_RELOC(ANDES, R_RISCV_NDS_BRANCH_10, 241)
/freebsd/sys/contrib/device-tree/src/riscv/andes/
H A Dqilai-voyager.dts3 * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
H A Dqilai.dtsi3 * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dandes_vector.h1 //===----- andes_vector.h - Andes Vector definitions ----------------------===//
/freebsd/contrib/llvm-project/clang/include/clang/Sema/
H A DSemaRISCV.h54 /// Indicate RISC-V Andes vector builtin functions enabled or not.
/freebsd/contrib/llvm-project/clang/utils/TableGen/
H A DTableGen.cpp324 "gen-riscv-andes-vector-builtins",
327 "gen-riscv-andes-vector-builtin-codegen",
330 "gen-riscv-andes-vector-builtin-sema",
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVFixupKinds.h63 // Andes specific fixups
H A DRISCVAsmBackend.cpp88 // Andes fixups in getFixupKindInfo()
766 VendorIdentifier = "ANDES"; in maybeAddVendorReloc()
/freebsd/contrib/file/magic/Magdir/
H A Delf247 >18 leshort 167 Andes embedded RISC,
/freebsd/lib/clang/libclang/
H A DMakefile1295 ${CLANG_TBLGEN} -gen-riscv-andes-vector-builtin-codegen \
1302 ${CLANG_TBLGEN} -gen-riscv-andes-vector-builtin-sema \
1309 ${CLANG_TBLGEN} -gen-riscv-andes-vector-builtins \
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp798 {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
/freebsd/sys/contrib/device-tree/Bindings/
H A Dvendor-prefixes.yaml130 description: Andes Technology Corporation
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DRISCV.cpp1363 // Andes Vector builtins are handled from here. in EmitRISCVBuiltinExpr()
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DELF.h266 EM_NDS32 = 167, // Andes Technology compact code size embedded RISC

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