Searched full:aarch32 (Results 1 – 17 of 17) sorted by relevance
13 …"PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CO…20 …"PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/…
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The45 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses60 no offset applied and do not sample the instruction set state in AArch3262 in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
3 * AArch32 user helpers.11 * reasons with 32 bit (aarch32) applications that need them.
3 * AArch32 sigreturn code.
146 * Create and map the vectors page for AArch32 tasks.
468 * AArch32 also requires breakpoints of length 2 for Thumb. in arch_build_bp_info()527 * AArch32 tasks expect some simple alignment fixups, so emulate in hw_breakpoint_arch_parse()
613 /* AARCH32 compat mode */ in arch_stack_walk_user()
20 /* Required for AArch32 compatibility. */
7 * Test that KVM handles the AArch64 views of the AArch32 ID registers as RAZ
469 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */ in test_vm_ftr_id_regs()
11 #define ARMV8_PMU_INSTR_IDX 32 /* Not accessible from AArch32 */
237 threshold_max will also read as 0 on aarch32 guests, even if the host
148 * an AArch32 fault, it means we managed to trap an EL0 fault. in inject_abt64()
40 * documented in the ARM AArch32 ELF psABI (IHI 0044).
453 compatibilidade voltadas para o espaço do usuário de 32 bits (AArch32):
484 (AArch32): ``arch/arm64/tools/syscall_32.tbl``. Dovete aggiungere una riga
1862 .args[2] = pt_fmt, /* 0: LPAE AArch32 - 1: AArch64 */ in qcom_scm_iommu_set_pt_format()