| /linux/arch/arm64/kvm/hyp/nvhe/ |
| H A D | sys_regs.c | 294 * Accessor for AArch32 feature id registers.
296 * The value of these registers is "unknown" according to the spec if AArch32
342 /* Mark the specified system register as an AArch32 feature id register. */
343 #define AARCH32(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch32 } macro
379 /* AArch64 mappings of the AArch32 ID registers */
381 AARCH32(SYS_ID_PFR0_EL1),
382 AARCH32(SYS_ID_PFR1_EL1),
383 AARCH32(SYS_ID_DFR0_EL1),
384 AARCH32(SYS_ID_AFR0_EL1),
385 AARCH32(SYS_ID_MMFR0_EL1),
[all …]
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| H A D | pkvm.c | 67 /* No support for AArch32. */ in pvm_init_traps_hcr()
138 /* No AArch32 support for protected guests. */ in pkvm_check_pvm_cpu_features()
139 if (kvm_has_feat(kvm, ID_AA64PFR0_EL1, EL0, AARCH32) || in pkvm_check_pvm_cpu_features()
140 kvm_has_feat(kvm, ID_AA64PFR0_EL1, EL1, AARCH32)) in pkvm_check_pvm_cpu_features()
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| H A D | switch.c | 218 * AArch32. The ARMv8 architecture does not give the hypervisor a in fixup_guest_exit()
219 * mechanism to prevent a guest from dropping to AArch32 EL0 if in fixup_guest_exit()
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| /linux/arch/arm64/include/asm/ |
| H A D | ptrace.h | 35 /* AArch32-specific ptrace requests */
45 /* SPSR_ELx bits for exceptions taken from AArch32 */
77 /* AArch32 CPSR bits, as seen in AArch32 */
103 /* sizeof(struct user) for AArch32 */
106 /* Architecturally defined mapping between AArch32 and AArch64 registers */
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| H A D | elf.h | 204 /* AArch32 registers. */
214 /* AArch32 EABI. */
264 /* No known properties for AArch32 yet */ in arch_parse_elf_property()
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| H A D | debug-monitors.h | 42 /* AArch32 */
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| H A D | mmu.h | 10 #define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */
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| H A D | ftrace.h | 193 * Because AArch32 mode does not share the same syscall table with AArch64,
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| /linux/arch/arm64/kvm/hyp/ |
| H A D | exception.c | 76 * of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx
77 * layouts, so we don't need to shuffle these for exceptions from AArch32 EL0.
80 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
176 * For the SPSR layout seen from AArch32, see:
180 * For the SPSR_ELx layout for AArch32 seen from AArch64, see:
183 * Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from
218 // SS does not exist in AArch32, so ignore in get_except32_cpsr()
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| H A D | instruction.json | 13 …"PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CO…
20 …"PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/…
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| /linux/Documentation/trace/coresight/ |
| H A D | coresight-cpu-debug.rst | 43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
45 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
60 no offset applied and do not sample the instruction set state in AArch32
62 in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
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| /linux/arch/arm64/kernel/ |
| H A D | kuser32.S | 3 * AArch32 user helpers.
11 * reasons with 32 bit (aarch32) applications that need them.
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| H A D | sigreturn32.S | 3 * AArch32 sigreturn code.
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| H A D | ptrace.c | 1812 /* Calculate the number of AArch32 registers contained in count */ in compat_gpr_set()
1965 .name = "aarch32", .e_machine = EM_ARM,
2023 .name = "aarch32", .e_machine = EM_ARM,
2329 * purpose register (ip/r12 for AArch32, x7 for AArch64) in the tracee in report_syscall()
2404 * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which is
2409 * Note that this follows the SPSR_ELx format, not the AArch32 PSR format.
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| /linux/drivers/firmware/efi/ |
| H A D | cper-arm.c | 21 "AArch32 general purpose registers",
22 "AArch32 EL1 context registers",
23 "AArch32 EL2 context registers",
24 "AArch32 secure context registers",
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| /linux/lib/raid6/ |
| H A D | recov_neon_inner.c | 12 * AArch32 does not provide this intrinsic natively because it does not
13 * implement the underlying instruction. AArch32 only provides a 64-bit
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| /linux/arch/arm64/kvm/hyp/vhe/ |
| H A D | Makefile | 12 obj-y += ../vgic-v3-sr.o ../aarch32.o ../vgic-v2-cpuif-proxy.o ../entry.o \
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| /linux/arch/arm64/include/uapi/asm/ |
| H A D | signal.h | 20 /* Required for AArch32 compatibility. */
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| H A D | fcntl.h | 21 * Using our own definitions for AArch32 (compat) support.
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| /linux/arch/arm64/ |
| H A D | Kconfig | 623 This option removes the AES hwcap for aarch32 user-space to
642 When running a compat (AArch32) userspace on an affected Cortex-A53
681 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
690 from AArch32 userspace.
1374 The system will use 16KB pages support. AArch32 emulation
1384 look-up. AArch32 emulation requires applications compiled
1706 kernel at EL1. AArch32-specific components such as system calls,
1711 that you will only be able to execute AArch32 binaries that were compiled
1815 instructions for AArch32 userspace code. When this option is
1826 AArch32 EL0, and is deprecated in ARMv8.
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| /linux/crypto/ |
| H A D | aegis128-neon-inner.c | 178 * AArch32 does not provide these intrinsics natively because it does not
179 * implement the underlying instructions. AArch32 only provides 64-bit
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| /linux/drivers/char/tpm/ |
| H A D | tpm_crb_ffa.c | 49 * are using the AArch32 or AArch64 SMC calling convention with register usage
358 /* if TPM is aarch32 use 32-bit SMCs */ in tpm_crb_ffa_probe()
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| /linux/arch/arm64/kvm/ |
| H A D | sys_regs.c | 43 * For AArch32, we only take care of what is being trapped. Anything
600 * for both AArch64 and AArch32 accesses.
621 if (p->Op0 == 0) { /* AArch32 */ in access_gic_sgi()
1366 /* The LC bit is RES1 when AArch32 is not supported */ in set_pmcr()
1890 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any in aa32_id_visibility()
3129 /* AArch64 mappings of the AArch32 ID registers */
3663 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */
4280 * AArch32 debug register mappings
4282 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
4283 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
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| /linux/tools/testing/selftests/kvm/arm64/ |
| H A D | aarch32_id_regs.c | 7 * Test that KVM handles the AArch64 views of the AArch32 ID registers as RAZ
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| /linux/arch/arm64/kernel/probes/ |
| H A D | uprobes.c | 48 /* TODO: Currently we do not support AARCH32 instruction probing */ in arch_uprobe_analyze_insn()
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