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Searched +full:axi4 +full:- +full:lite (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/staging/axis-fifo/
H A Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
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/linux/Documentation/devicetree/bindings/misc/
H A Dxlnx,sd-fec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cvetic, Dragan <dragan.cvetic@amd.com>
11 - Erim, Salih <salih.erim@amd.com>
15 which provides high-throughput LDPC and Turbo Code implementations.
17 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
23 const: xlnx,sd-fec-1.1
33 - description: Main processing clock for processing core
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/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,pr-decoupler.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 - $ref: fpga-bridge.yaml#
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
24 bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
28 Please refer to fpga-region.txt and fpga-bridge.txt in this directory for
34 - items:
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/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
14 traffic from compliant camera sensors and send the output as AXI4 Stream
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
19 AXI4 Stream video data.
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/linux/Documentation/devicetree/bindings/media/
H A Dallegro,al5e.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
23 - items:
24 - const: allegro,al5e-1.1
25 - const: allegro,al5e
26 - items:
27 - const: allegro,al5d-1.1
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/linux/Documentation/devicetree/bindings/gpio/
H A Dxlnx,gpio-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neeli Srinivas <srinivas.neeli@amd.com>
14 to an AXI4-Lite interface. The AXI GPIO can be configured as either
15 a single or a dual-channel device. The width of each channel is
22 - xlnx,xps-gpio-1.00.a
27 "#gpio-cells":
33 gpio-controller: true
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/linux/Documentation/networking/device_drivers/can/ctu/
H A Dctucanfd-driver.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
10 ------------------------
19 `Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20 and Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21 `QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
23 `PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
33 version of emulation support can be cloned from ctu-canfd branch of QEMU local
34 development `repository <https://gitlab.fel.cvut.cz/canbus/qemu-canbus>`_.
38 ---------------
59 it allows for device hot-plug.
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/linux/drivers/misc/
H A Dxilinx_sdfec.c1 // SPDX-License-Identifier: GPL-2.0
65 /* Write Only - Interrupt Enable Register */
67 /* Write Only - Interrupt Disable Register */
69 /* Read Only - Interrupt Mask Register */
101 /* Write Only - ECC Interrupt Enable Register */
103 /* Write Only - ECC Interrupt Disable Register */
105 /* Read Only - ECC Interrupt Mask Register */
169 * struct xsdfec_clks - For managing SD-FEC clocks
171 * @axi_clk: AXI4-Lite memory-mapped clock
172 * @din_words_clk: DIN Words AXI4-Stream Slave clock
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/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
178 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
179 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
206 /* Transmit inter-frame gap adjustment value */
240 /* In-Band FCS enable (FCS not stripped) */
256 /* In-Band FCS enable (FCS not generated) */
260 /* Inter-frame gap adjustment enable */
282 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
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/linux/drivers/dma/xilinx/
H A Dxilinx_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
18 * registers are accessed through an AXI4-Lite slave interface.
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
26 * Access (DMA) between a memory-mapped source address and a memory-mapped
30 * Xilinx IP that provides high-bandwidth direct memory access between
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/linux/drivers/i2c/busses/
H A Di2c-xiic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
56 * struct xiic_i2c - Internal representation of the XIIC I2C bus
67 * @endianness: big/little-endian byte order
68 * @clk: Pointer to AXI4-lite input clock
106 * struct timing_regs - AXI I2C timing registers that depend on I2C spec
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/linux/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
272 ARM 64-bit (AArch64) Linux support.
280 # required due to use of the -Zfixed-x18 flag.
283 # -Zsanitizer=shadow-call-stack flag.
293 depends on $(cc-option,-fpatchable-function-entry=2)
319 # VA_BITS - PAGE_SHIFT - 3
397 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
402 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
452 at stage-2.
460 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
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