| /linux/drivers/bus/ |
| H A D | bt1-axi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 AXI-bus driver
35 * struct bt1_axi - Baikal-T1 AXI-bus private data
37 * @qos_regs: AXI Interconnect QoS tuning registers.
38 * @sys_regs: Baikal-T1 System Controller registers map.
40 * @aclk: AXI reference clock.
41 * @arst: AXI Interconnect reset line.
60 struct bt1_axi *axi = data; in bt1_axi_isr() local
63 regmap_read(axi->sys_regs, BT1_AXI_WERRL, &low); in bt1_axi_isr()
64 regmap_read(axi->sys_regs, BT1_AXI_WERRH, &high); in bt1_axi_isr()
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # Bus Devices
6 menu "Bus devices"
24 bool "ARM Integrator Logic Module bus"
29 Say y here to enable support for the ARM Logic Module bus
33 tristate "Broadcom STB GISB bus arbiter"
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
39 and internal bus master decoding.
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | baikal,bt1-axi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
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| H A D | brcm,bus-axi.txt | 1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
13 them manually through device tree. Use an interrupt-map to specify the
14 IRQ used by the devices on the bus. The first address is just an index,
17 The top-level axi bus may contain children representing attached cores
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
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| H A D | starfive,jh7110-aoncrg.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-aoncrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
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| H A D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
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| H A D | starfive,jh7110-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kevin Xie <kevin.xie@starfivetech.com>
13 - $ref: plda,xpressrich3-axi-common.yaml#
17 const: starfive,jh7110-pcie
21 - description: NOC bus clock
22 - description: Transport layer clock
23 - description: AXI MST0 clock
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | snps,dwcmshc-sdhci.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
16 - items:
17 - const: rockchip,rk3576-dwcmshc
18 - const: rockchip,rk3588-dwcmshc
19 - enum:
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| /linux/Documentation/admin-guide/perf/ |
| H A D | imx-ddr.rst | 17 (AXI filter setting) fields of the perf_event_attr structure, see /sys/bus/event_source/
19 hardware supported that can be used with perf tool, see /sys/bus/event_source/
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for
33 un-supported, and value 1 for supported.
37 --AXI_ID defines AxID matching value.
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | snps,dwc-qos-ethernet.txt | 7 IP block. The IP supports multiple options for bus type, clocking and reset
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | marvell,mmp2-ccic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <lkundrak@v3.sk>
15 pattern: '^camera@[a-f0-9]+$'
18 const: marvell,mmp2-ccic
26 power-domains:
30 $ref: /schemas/graph.yaml#/$defs/port-base
35 $ref: video-interfaces.yaml#
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| /linux/drivers/pci/controller/cadence/ |
| H A D | pcie-cadence.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
42 /* Endpoint Bus and Device Number Register */
117 (((aperture) - 2) << ((bar) * 8))
150 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
155 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
160 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ argument
161 (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
163 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
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| /linux/Documentation/devicetree/bindings/soc/imx/ |
| H A D | fsl,imx8mm-disp-blk-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
26 '#power-domain-cells':
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| /linux/drivers/clk/baikal-t1/ |
| H A D | clk-ccu-div.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU Dividers clock driver
12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
18 #include <linux/clk-provider.h>
19 #include <linux/reset-controller.h>
26 #include <dt-bindings/clock/bt1-ccu.h>
28 #include "ccu-div.h"
29 #include "ccu-rst.h"
124 * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
126 * clocking a bus between CPU cores and the rest of the SoC components, while
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| /linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | stmmac_platform.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2007-2011 STMicroelectronics Ltd
26 * dwmac1000_validate_mcast_bins - validates the number of Multicast filter bins
57 * dwmac1000_validate_ucast_entries - validate the Unicast address entries
88 * stmmac_axi_setup - parse DT parameters for programming the AXI register
91 * if required, from device-tree the AXI internal register can be tuned
97 struct stmmac_axi *axi; in stmmac_axi_setup() local
99 np = of_parse_phandle(pdev->dev.of_node, "snps,axi-config", 0); in stmmac_axi_setup()
103 axi = devm_kzalloc(&pdev->dev, sizeof(*axi), GFP_KERNEL); in stmmac_axi_setup()
104 if (!axi) { in stmmac_axi_setup()
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | mediatek,spi-mtk-nor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
21 - $ref: /schemas/spi/spi-controller.yaml#
26 - enum:
27 - mediatek,mt8173-nor
28 - mediatek,mt8186-nor
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| H A D | adi,axi-spi-engine.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI SPI Engine Controller
10 The AXI SPI Engine controller is part of the SPI Engine framework[1] and
11 allows memory mapped access to the SPI Engine control bus. This allows it
18 - Michael Hennerich <Michael.Hennerich@analog.com>
19 - Nuno Sá <nuno.sa@analog.com>
22 - $ref: /schemas/spi/spi-controller.yaml#
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| /linux/drivers/dma/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
154 tristate "SA-11x0 DMA support"
159 Support the DMA engine found on Intel StrongARM SA-1100 and
160 SA-1110 SoCs. This DMA engine can only be used with on-chip
183 tristate "Synopsys DesignWare AXI DMA support"
189 Enable support for Synopsys DesignWare AXI DMA controller.
191 of lack 64 bit platform with Synopsys DW AXI DMAC.
220 This module can be found on Freescale Vybrid and LS-1 SoCs.
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| /linux/drivers/ata/ |
| H A D | ahci_mtk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
21 #define DRV_NAME "ahci-mtk"
48 struct mtk_ahci_plat *plat = hpriv->plat_data; in mtk_ahci_platform_resets()
51 /* reset AXI bus and PHY part */ in mtk_ahci_platform_resets()
52 plat->axi_rst = devm_reset_control_get_optional_exclusive(dev, "axi"); in mtk_ahci_platform_resets()
53 if (PTR_ERR(plat->axi_rst) == -EPROBE_DEFER) in mtk_ahci_platform_resets()
54 return PTR_ERR(plat->axi_rst); in mtk_ahci_platform_resets()
56 plat->sw_rst = devm_reset_control_get_optional_exclusive(dev, "sw"); in mtk_ahci_platform_resets()
57 if (PTR_ERR(plat->sw_rst) == -EPROBE_DEFER) in mtk_ahci_platform_resets()
58 return PTR_ERR(plat->sw_rst); in mtk_ahci_platform_resets()
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | microchip,sparx5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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| /linux/Documentation/devicetree/bindings/w1/ |
| H A D | amd,axi-1wire-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AMD AXI 1-wire bus host for programmable logic
10 - Kris Chaplin <kris.chaplin@amd.com>
14 const: amd,axi-1wire-host
26 - compatible
27 - reg
28 - clocks
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| /linux/drivers/net/ethernet/xilinx/ |
| H A D | xilinx_axienet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for Xilinx Axi Ethernet device driver.
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
73 /* Axi DMA Register definitions */
145 /* Axi Ethernet registers definition */
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
178 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
179 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
185 /* Bit Masks for Axi Ethernet RAF register */
204 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
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