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/linux/arch/x86/kvm/
H A Dlapic.c4 * Local APIC virtualization
30 #include <asm/apic.h>
61 * Enable local APIC timer advancement (tscdeadline mode only) with adaptive
81 static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);
82 static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data);
84 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) in kvm_lapic_set_reg() argument
86 apic_set_reg(apic->regs, reg_off, val); in kvm_lapic_set_reg()
89 static __always_inline u64 kvm_lapic_get_reg64(struct kvm_lapic *apic, int reg) in kvm_lapic_get_reg64() argument
91 return apic_get_reg64(apic->regs, reg); in kvm_lapic_get_reg64()
94 static __always_inline void kvm_lapic_set_reg64(struct kvm_lapic *apic, in kvm_lapic_set_reg64() argument
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/linux/arch/x86/kernel/apic/
H A Dinit.c2 #define pr_fmt(fmt) "APIC: " fmt
4 #include <asm/apic.h>
15 DEFINE_STATIC_CALL_NULL(apic_call_##__cb, *apic->__cb)
41 apic->__cb = __x86_apic_override.__cb
62 static_call_update(apic_call_##__cb, *apic->__cb)
85 /* Ensure that the default APIC has native_eoi populated */ in apic_setup_apic_calls()
86 apic->native_eoi = apic->eoi; in apic_setup_apic_calls()
91 void __init apic_install_driver(struct apic *driver) in apic_install_driver()
93 if (apic == driver) in apic_install_driver()
96 apic = driver; in apic_install_driver()
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H A Dapic_flat_64.c5 * Flat APIC subarch code.
13 #include <asm/apic.h>
32 static struct apic apic_physflat __ro_after_init = {
67 struct apic *apic __ro_after_init = &apic_physflat;
68 EXPORT_SYMBOL_GPL(apic);
H A Dvector.c3 * Local APIC related interfaces to support IOAPIC, MSI, etc.
6 * Moved from arch/x86/kernel/apic/io_apic.c.
19 #include <asm/apic.h>
136 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); in apic_update_irq_cfg()
671 return fwname && !strncmp(fwname, "IO-APIC-", 8) && in x86_fwspec_is_ioapic()
697 * if IRQ remapping is enabled. APIC IDs above 15 bits are in x86_vector_select()
762 * If the IO/APIC is disabled via config, kernel command line or in lapic_update_legacy_vectors()
792 * in the IO/APIC code. in lapic_assign_system_vectors()
838 /* Online the local APIC infrastructure and initialize the vectors */
978 * of the interrupt on the apic/system bus would be delayed in apic_force_complete_move()
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H A Dprobe_64.c5 * Generic APIC sub-arch probe layer.
12 #include <asm/apic.h>
16 /* Select the appropriate APIC driver */
19 struct apic **drv; in x86_64_probe_apic()
33 struct apic **drv; in default_acpi_madt_oem_check()
H A DMakefile3 # Makefile for local APIC drivers and for the IO-APIC code
10 obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_common.o apic_noop.o ipi.o vector.o init.o
18 # APIC probe will depend on the listing order here
H A Dapic_common.c2 * Common functions shared between the various APIC flavours
8 #include <asm/apic.h>
31 * Set up the logical destination ID when the APIC operates in logical
H A Dx2apic_cluster.c8 #include <asm/apic.h>
111 u32 apicid = apic->cpu_present_to_apicid(cpu_i); in prefill_clustermask()
147 u32 apicid = apic->cpu_present_to_apicid(cpu_i); in alloc_clustermask()
178 u32 phys_apicid = apic->cpu_present_to_apicid(cpu); in x2apic_prepare_cpu()
227 static struct apic apic_x2apic_cluster __ro_after_init = {
/linux/arch/x86/kernel/cpu/
H A Dtopology.c3 * CPU/APIC topology
5 * The APIC IDs describe the system topology in multiple domain levels.
7 * APIC ID is associated to the individual levels:
29 #include <asm/apic.h>
39 * Map cpu index to physical APIC ID
85 * Convert the APIC ID to a domain level ID by masking out the low bits
134 * longer supported, the real BSP APIC ID is the first one which is in check_for_real_bsp()
136 * CPU is the real BSP. If it is not, then do not register the APIC in check_for_real_bsp()
140 * The first APIC ID which is enumerated by firmware is detectable in check_for_real_bsp()
141 * because the boot CPU APIC ID is registered before that without in check_for_real_bsp()
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/linux/tools/testing/selftests/kvm/x86/
H A Dapic_bus_clock_test.c5 * Verify KVM correctly emulates the APIC bus frequency when the VMM configures
6 * the frequency via KVM_CAP_X86_APIC_BUS_CYCLES_NS. Start the APIC timer by
10 * of the expected value based on the time elapsed, the APIC bus frequency, and
14 #include "apic.h"
18 * Possible TDCR values with matching divide count. Used to modify APIC
150 "Setting of APIC bus frequency after vCPU is created should fail."); in run_apic_bus_clock_test()
162 printf("usage: %s [-h] [-d delay] [-f APIC bus freq]\n", name); in help()
164 printf("-d: Delay (in msec) guest uses to measure APIC bus frequency.\n"); in help()
165 printf("-f: The APIC bus frequency (in MHz) to be configured for the guest.\n"); in help()
172 * Arbitrarilty default to 25MHz for the APIC bus frequency, which is in main()
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H A Dvmx_apic_access_test.c10 * launched with a valid APIC-access address that is backed by a
13 * The second subtest sets the APIC-access address to a (valid) L1
57 /* Try to launch L2 with the memory-backed APIC-access address. */ in l1_guest_code()
64 /* Try to resume L2 with the unbacked APIC-access address. */ in l1_guest_code()
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dintel,ce4100-ioapic.yaml7 title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
16 into the processor itself and an external I/O APIC. Local APIC
18 from internal sources and from an external I/O APIC (ioapic).
26 This schema defines bindings for I/O APIC interrupt controller.
H A Dintel,ce4100-lapic.yaml13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
16 into the processor itself and an external I/O APIC. Local APIC
18 from internal sources and from an external I/O APIC (ioapic).
26 This schema defines bindings for local APIC interrupt controller.
/linux/Documentation/arch/x86/i386/
H A DIO-APIC.rst4 IO-APIC
9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
12 IO-APIC, interrupts from hardware will be delivered only to the
23 If your box boots fine with enabled IO-APIC IRQs, then your
28 0: 1360293 IO-APIC-edge timer
29 1: 4 IO-APIC-edge keyboard
32 14: 1448 IO-APIC-edge ide0
33 16: 28232 IO-APIC-level Intel EtherExpress Pro 10/100 Ethernet
34 17: 51304 IO-APIC-level eth0
97 board does not do default daisy-chaining. (or the IO-APIC has the PIRQ pins
/linux/arch/x86/kernel/
H A Dirqinit.c27 #include <asm/apic.h>
35 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
40 * The IO-APIC gives us many more interrupt sources. Most of these
45 * IO-APIC registers.
60 * Try to set up the through-local-APIC virtual wire mode earlier. in init_ISA_irqs()
62 * On some 32-bit UP machines, whose APIC has been disabled by BIOS in init_ISA_irqs()
83 * these IRQs are handled by more modern controllers like IO-APIC, in init_IRQ()
/linux/arch/x86/kvm/svm/
H A Davic.c37 * instead of its ID (a.k.a. its default APIC ID), as KVM is guaranteed a fast
42 * guest physical APIC ID (limited by the size of the physical ID table), and
157 if (x2avic_enabled && (!vcpu || apic_x2apic_mode(vcpu->arch.apic))) in __avic_get_max_physical_id()
163 * Despite its name, KVM_CAP_MAX_VCPU_ID represents the maximum APIC ID in __avic_get_max_physical_id()
164 * plus one, so the max possible APIC ID is one less than that. in __avic_get_max_physical_id()
191 * KVM uses a per-VM "scratch" page to back the APIC memslot, because in avic_activate_vmcb()
194 * have their local APIC hardware-disabled or are in x2APIC mode, i.e. in avic_activate_vmcb()
195 * even if one or more vCPUs' APIC MMIO BAR is effectively disabled. in avic_activate_vmcb()
198 * KVM's page tables, i.e. in the leaf SPTE for the APIC memslot, and in avic_activate_vmcb()
200 * vCPU's virtual APIC page. If xAVIC is not enabled (APIC is either in avic_activate_vmcb()
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/linux/Documentation/virt/kvm/x86/
H A Dhypercalls.rst99 specifying APIC ID (a1) of the vcpu to be woken up. An additional argument (a0)
147 - a0: lower part of the bitmap of destination APIC IDs
148 - a1: higher part of the bitmap of destination APIC IDs
149 - a2: the lowest APIC ID in bitmap
150 - a3: APIC ICR
156 a0 corresponds to the APIC ID in the third argument (a2), bit 1
157 corresponds to the APIC ID a2+1, and so on.
168 a0: destination APIC ID
/linux/Documentation/arch/x86/
H A Dtopology.rst69 and deduced from the APIC IDs of the cores in the package.
88 - On Intel, the first APIC ID of the list of CPUs sharing the Last Level
210 The shifts from the APIC ID for the Socket ID is calculated from the
217 Unless Extended APIC ID is supported, the APIC ID used to find the
221 The topology parsing continues to detect if Extended APIC ID is
225 4) CPUID leaf 0x8000001E [Extended APIC ID, Core Identifiers, Node Identifiers]
228 The support for Extended APIC ID can be detected by checking for the
232 If Topology Extensions is supported, the APIC ID from `ExtendedApicId`
238 0x80000026 or CPUID leaf 0xB, the shifts from the APIC ID for the Core
310 the shifts from the APIC ID required to compute the Core ID.
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/linux/arch/x86/xen/
H A Dapic.c6 #include <asm/apic.h>
14 static unsigned int xen_io_apic_read(unsigned apic, unsigned reg) in xen_io_apic_read() argument
19 apic_op.apic_physbase = mpc_ioapic_addr(apic); in xen_io_apic_read()
29 return apic << 24; in xen_io_apic_read()
113 static struct apic xen_pv_apic __ro_after_init = {
/linux/arch/x86/include/asm/
H A Dio_apic.h11 * Intel IO-APIC support for SMP and UP systems.
17 * The structure of the IO-APIC:
128 * If we use the IO-APIC for IRQ routing, disable automatic
162 extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
165 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) in io_apic_read() argument
167 return x86_apic_ops.io_apic_read(apic, reg); in io_apic_read()
H A Dvmxfeatures.h16 /* Pin-Based VM-Execution Controls, EPT/VPID, APIC and VM-Functions, word 0 */
30 /* Aggregated APIC features 24-27 */
31 #define VMX_FEATURE_FLEXPRIORITY ( 0*32+ 24) /* "flexpriority" TPR shadow + virt APIC */
32 #define VMX_FEATURE_APICV ( 0*32+ 25) /* "apicv" TPR shadow + APIC reg virt + virt intr del…
62 #define VMX_FEATURE_VIRT_APIC_ACCESSES ( 2*32+ 0) /* "vapic" Virtualize memory mapped APIC accesse…
70 …RE_APIC_REGISTER_VIRT ( 2*32+ 8) /* "vapic_reg" Hardware emulation of reads to the virtual-APIC */
/linux/arch/x86/mm/
H A Dsrat.c23 #include <asm/apic.h>
55 …printk(KERN_INFO "SRAT: PXM %u -> APIC 0x%04x -> Node %u skipped apicid that is too big\n", pxm, a… in acpi_numa_x2apic_affinity_init()
61 pr_debug("SRAT: PXM %u -> APIC 0x%04x -> Node %u\n", pxm, apic_id, node); in acpi_numa_x2apic_affinity_init()
95 …printk(KERN_INFO "SRAT: PXM %u -> APIC 0x%02x -> Node %u skipped apicid that is too big\n", pxm, a… in acpi_numa_processor_affinity_init()
102 pr_debug("SRAT: PXM %u -> APIC 0x%02x -> Node %u\n", pxm, apic_id, node); in acpi_numa_processor_affinity_init()
/linux/Documentation/PCI/
H A Dboot-interrupts.rst13 interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a
15 MSI interrupts. If the IO-APIC is disabled (via the mask bits in the
16 IO-APIC table entries), the messages are routed to the legacy PCH. This
18 did not support the IO-APIC and for boot. Intel in the past has used the
80 devices. IO-APIC is only in the PCH. Devices connected to the Core IO's
105 PCH - they are either converted into MSI via the integrated IO-APIC
106 (if the IO-APIC mask bit is clear in the appropriate entries)
/linux/tools/testing/selftests/kvm/lib/x86/
H A Dapic.c6 #include "apic.h"
19 /* Per SDM: to enable xAPIC when in x2APIC must first disable APIC */ in xapic_enable()
30 * APIC software enabled bit=0. It must be enabled in addition to the in xapic_enable()
/linux/Documentation/devicetree/bindings/x86/
H A Dce4100.txt6 Many of the "generic" devices like HPET or IO APIC have the ce4100
38 Local APIC ID, the unique number assigned to each processor by
52 If the OS is using the IO-APIC for interrupt routing then the reported

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