| /linux/arch/x86/kvm/ |
| H A D | lapic.c | 4 * Local APIC virtualization
30 #include <asm/apic.h>
61 * Enable local APIC timer advancement (tscdeadline mode only) with adaptive
81 static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);
82 static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data);
84 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) in kvm_lapic_set_reg() argument
86 apic_set_reg(apic->regs, reg_off, val); in kvm_lapic_set_reg()
89 static __always_inline u64 kvm_lapic_get_reg64(struct kvm_lapic *apic, int reg) in kvm_lapic_get_reg64() argument
91 return apic_get_reg64(apic->regs, reg); in kvm_lapic_get_reg64()
94 static __always_inline void kvm_lapic_set_reg64(struct kvm_lapic *apic, in kvm_lapic_set_reg64() argument
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| H A D | lapic.h | 7 #include <asm/apic.h>
79 * APIC register page. The layout matches the register layout seen by
114 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
124 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
142 int kvm_x2apic_icr_write_fast(struct kvm_lapic *apic, u64 data);
152 u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
154 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) in kvm_lapic_set_irr() argument
156 apic_set_vector(vec, apic->regs + APIC_IRR); in kvm_lapic_set_irr()
161 apic->irr_pending = true; in kvm_lapic_set_irr()
164 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) in kvm_lapic_get_reg() argument
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| /linux/arch/x86/kernel/apic/ |
| H A D | apic.c | 3 * Local APIC handling, local APIC timers
13 * Mikael Pettersson : Power Management for UP-APIC.
53 #include <asm/apic.h>
85 * Hypervisor supports 15 bits of APIC ID in MSI Extended Destination ID
98 /* Local APIC was disabled by the BIOS and enabled by the kernel */
105 * local APIC. Before entering Symmetric I/O Mode, either
111 /* NMI and 8259 INTR go through APIC */ in imcr_pic_to_apic()
123 * Knob to control our willingness to enable the local APIC.
130 * APIC command line parameters
155 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
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| H A D | init.c | 2 #define pr_fmt(fmt) "APIC: " fmt
4 #include <asm/apic.h>
15 DEFINE_STATIC_CALL_NULL(apic_call_##__cb, *apic->__cb)
41 apic->__cb = __x86_apic_override.__cb
62 static_call_update(apic_call_##__cb, *apic->__cb)
85 /* Ensure that the default APIC has native_eoi populated */ in apic_setup_apic_calls()
86 apic->native_eoi = apic->eoi; in apic_setup_apic_calls()
91 void __init apic_install_driver(struct apic *driver) in apic_install_driver()
93 if (apic == driver) in apic_install_driver()
96 apic = driver; in apic_install_driver()
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| H A D | io_apic.c | 3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
25 * - SiS APIC rmw bug:
67 #include <asm/apic.h>
90 int apic, pin; member
112 /* I/O APIC config */
114 /* IO APIC gsi routing info */
193 /* disable IO-APIC */ in parse_noapic()
204 apic_pr_verbose("Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n", in mp_save_irq()
264 static inline void io_apic_eoi(unsigned int apic, unsigned int vector) in io_apic_eoi() argument
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| H A D | x2apic_savic.c | 15 #include <asm/apic.h>
50 * When Secure AVIC is enabled, RDMSR/WRMSR of the APIC registers
53 * can read/write the x2APIC register in the guest APIC backing page.
57 * handling the APIC register reads/writes in the #VC exception handler,
58 * the read() and write() callbacks directly read/write the APIC register
59 * from/to the vCPU's APIC backing page.
95 "APIC register read offset 0x%x not aligned at 16 bytes", reg)) in savic_read()
114 "Misaligned APIC_IRR/ALLOWED_IRR APIC register read offset 0x%x", reg)) in savic_read()
127 * updates the APIC_IRR in the APIC backing page of the vCPU. In addition,
347 * Before Secure AVIC is enabled, APIC MSR reads are intercepted. in savic_setup()
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| H A D | apic_flat_64.c | 5 * Flat APIC subarch code.
13 #include <asm/apic.h>
32 static struct apic apic_physflat __ro_after_init = {
67 struct apic *apic __ro_after_init = &apic_physflat;
68 EXPORT_SYMBOL_GPL(apic);
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| H A D | vector.c | 3 * Local APIC related interfaces to support IOAPIC, MSI, etc.
6 * Moved from arch/x86/kernel/apic/io_apic.c.
19 #include <asm/apic.h>
136 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); in apic_update_irq_cfg()
671 return fwname && !strncmp(fwname, "IO-APIC-", 8) && in x86_fwspec_is_ioapic()
697 * if IRQ remapping is enabled. APIC IDs above 15 bits are in x86_vector_select()
762 * If the IO/APIC is disabled via config, kernel command line or in lapic_update_legacy_vectors()
792 * in the IO/APIC code. in lapic_assign_system_vectors()
838 /* Online the local APIC infrastructure and initialize the vectors */
978 * of the interrupt on the apic/system bus would be delayed in apic_force_complete_move()
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| H A D | probe_64.c | 5 * Generic APIC sub-arch probe layer.
12 #include <asm/apic.h>
16 /* Select the appropriate APIC driver */
19 struct apic **drv; in x86_64_probe_apic()
33 struct apic **drv; in default_acpi_madt_oem_check()
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| H A D | Makefile | 3 # Makefile for local APIC drivers and for the IO-APIC code
10 obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_common.o apic_noop.o ipi.o vector.o init.o
18 # APIC probe will depend on the listing order here
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| H A D | x2apic_phys.c | 10 static struct apic apic_x2apic_phys;
16 if (apic->x2apic_set_max_apicid) in x2apic_set_max_apicid()
17 apic->max_apic_id = apicid; in x2apic_set_max_apicid()
124 return apic == &apic_x2apic_phys; in x2apic_phys_probe()
132 static struct apic apic_x2apic_phys __ro_after_init = {
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| /linux/arch/x86/kernel/cpu/ |
| H A D | topology.c | 3 * CPU/APIC topology
5 * The APIC IDs describe the system topology in multiple domain levels.
7 * APIC ID is associated to the individual levels:
29 #include <asm/apic.h>
39 * Map cpu index to physical APIC ID
89 * Convert the APIC ID to a domain level ID by masking out the low bits
138 * longer supported, the real BSP APIC ID is the first one which is in check_for_real_bsp()
140 * CPU is the real BSP. If it is not, then do not register the APIC in check_for_real_bsp()
144 * The first APIC ID which is enumerated by firmware is detectable in check_for_real_bsp()
145 * because the boot CPU APIC ID is registered before that without in check_for_real_bsp()
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| H A D | acrn.c | 15 #include <asm/apic.h>
48 * The hypervisor requires that the APIC EOI should be acked. in DEFINE_IDTENTRY_SYSVEC()
49 * If the APIC EOI is not acked, the APIC ISR bit for the in DEFINE_IDTENTRY_SYSVEC()
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| /linux/arch/x86/include/asm/ |
| H A D | apic.h | 35 * up by using apic=verbose for more information and apic=debug for _lots_
36 * of information. apic_verbosity is defined in apic.c
78 * With 82489DX we can't rely on apic feature bit
80 * such an apic chip so we assume that SMP configuration
268 * Generic APIC sub-arch data struct.
274 struct apic { struct
303 /* The limit of the APIC ID space. */
345 * Pointer to the local APIC driver in use on this system (there's
349 extern struct apic *apic;
352 * APIC drivers are probed based on how they are listed in the .apicdrivers
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| H A D | io_apic.h | 11 * Intel IO-APIC support for SMP and UP systems.
17 * The structure of the IO-APIC:
128 * If we use the IO-APIC for IRQ routing, disable automatic
162 extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
165 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) in io_apic_read() argument
167 return x86_apic_ops.io_apic_read(apic, reg); in io_apic_read()
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| /linux/drivers/iommu/ |
| H A D | hyperv-iommu.c | 17 #include <asm/apic.h>
30 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
31 * Redirection Table. Hyper-V exposes one single IO-APIC and so define
32 * 24 IO APIC remmapping entries.
89 * Hypver-V IO APIC irq affinity should be in the scope of in hyperv_irq_remapping_alloc()
107 /* Claim the only I/O APIC emulated by Hyper-V */ in hyperv_irq_remapping_select()
159 * IO-APIC and so IO-APIC only accepts 8-bit APIC ID. in hyperv_prepare_irq_remapping()
160 * Cpu's APIC ID is read from ACPI MADT table and APIC IDs in hyperv_prepare_irq_remapping()
162 * APIC ID reflects cpu topology. There maybe some APIC ID in hyperv_prepare_irq_remapping()
165 * into ioapic_max_cpumask if its APIC ID is less than 256. in hyperv_prepare_irq_remapping()
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | intel,ce4100-ioapic.yaml | 7 title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
16 into the processor itself and an external I/O APIC. Local APIC
18 from internal sources and from an external I/O APIC (ioapic).
26 This schema defines bindings for I/O APIC interrupt controller.
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| H A D | intel,ce4100-lapic.yaml | 13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
16 into the processor itself and an external I/O APIC. Local APIC
18 from internal sources and from an external I/O APIC (ioapic).
26 This schema defines bindings for local APIC interrupt controller.
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| /linux/Documentation/arch/x86/i386/ |
| H A D | IO-APIC.rst | 4 IO-APIC
9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
12 IO-APIC, interrupts from hardware will be delivered only to the
23 If your box boots fine with enabled IO-APIC IRQs, then your
28 0: 1360293 IO-APIC-edge timer
29 1: 4 IO-APIC-edge keyboard
32 14: 1448 IO-APIC-edge ide0
33 16: 28232 IO-APIC-level Intel EtherExpress Pro 10/100 Ethernet
34 17: 51304 IO-APIC-level eth0
97 board does not do default daisy-chaining. (or the IO-APIC has the PIRQ pins
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| /linux/arch/x86/kernel/ |
| H A D | irqinit.c | 27 #include <asm/apic.h>
35 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
40 * The IO-APIC gives us many more interrupt sources. Most of these
45 * IO-APIC registers.
60 * Try to set up the through-local-APIC virtual wire mode earlier. in init_ISA_irqs()
62 * On some 32-bit UP machines, whose APIC has been disabled by BIOS in init_ISA_irqs()
83 * these IRQs are handled by more modern controllers like IO-APIC, in init_IRQ()
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| H A D | smpboot.c | 26 * Ingo Molnar : Added APIC timers, based on code
77 #include <asm/apic.h>
184 * point before an INIT_deassert IPI reaches the local APIC, so it in ap_starting()
185 * is now safe to touch the local APIC. in ap_starting()
187 * Set up this CPU, first the APIC, which is probably redundant on in ap_starting()
673 /* Be paranoid about clearing APIC errors. */ in send_init_sequence()
709 * Determine this based on the APIC version. in wakeup_secondary_cpu_via_init()
710 * If we don't have an integrated APIC, don't send the STARTUP IPIs. in wakeup_secondary_cpu_via_init()
769 pr_err("APIC never delivered???\n"); in wakeup_secondary_cpu_via_init()
771 pr_err("APIC delivery error (%lx)\n", accept_status); in wakeup_secondary_cpu_via_init()
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| /linux/arch/x86/kvm/svm/ |
| H A D | avic.c | 36 * instead of its ID (a.k.a. its default APIC ID), as KVM is guaranteed a fast
41 * guest physical APIC ID (limited by the size of the physical ID table), and
173 * achieved using AVIC doorbell. KVM disables the APIC access page in avic_activate_vmcb()
177 if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) { in avic_activate_vmcb()
184 * Flush the TLB, the guest may have inserted a non-APIC in avic_activate_vmcb()
312 return __sme_set(__pa(svm->vcpu.arch.apic->regs)); in avic_get_backing_page_address()
347 vcpu->arch.apic->apicv_active = false; in avic_init_backing_page()
354 if (WARN_ON_ONCE(!vcpu->arch.apic->regs)) in avic_init_backing_page()
375 /* Setting AVIC backing page address in the phy APIC ID table */ in avic_init_backing_page()
411 vcpu->arch.apic->irr_pending = true; in avic_kick_vcpu()
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| /linux/Documentation/virt/kvm/x86/ |
| H A D | hypercalls.rst | 99 specifying APIC ID (a1) of the vcpu to be woken up. An additional argument (a0)
147 - a0: lower part of the bitmap of destination APIC IDs
148 - a1: higher part of the bitmap of destination APIC IDs
149 - a2: the lowest APIC ID in bitmap
150 - a3: APIC ICR
156 a0 corresponds to the APIC ID in the third argument (a2), bit 1
157 corresponds to the APIC ID a2+1, and so on.
168 a0: destination APIC ID
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| /linux/Documentation/arch/x86/ |
| H A D | topology.rst | 69 and deduced from the APIC IDs of the cores in the package.
88 - On Intel, the first APIC ID of the list of CPUs sharing the Last Level
210 The shifts from the APIC ID for the Socket ID is calculated from the
217 Unless Extended APIC ID is supported, the APIC ID used to find the
221 The topology parsing continues to detect if Extended APIC ID is
225 4) CPUID leaf 0x8000001E [Extended APIC ID, Core Identifiers, Node Identifiers]
228 The support for Extended APIC ID can be detected by checking for the
232 If Topology Extensions is supported, the APIC ID from `ExtendedApicId`
238 0x80000026 or CPUID leaf 0xB, the shifts from the APIC ID for the Core
310 the shifts from the APIC ID required to compute the Core ID.
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| /linux/arch/x86/xen/ |
| H A D | apic.c | 6 #include <asm/apic.h>
14 static unsigned int xen_io_apic_read(unsigned apic, unsigned reg) in xen_io_apic_read() argument
19 apic_op.apic_physbase = mpc_ioapic_addr(apic); in xen_io_apic_read()
29 return apic << 24; in xen_io_apic_read()
113 static struct apic xen_pv_apic __ro_after_init = {
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