Searched full:apb3 (Results 1 – 14 of 14) sorted by relevance
/linux/Documentation/devicetree/bindings/net/pcs/ |
H A D | snps,dw-xpcs.yaml | 22 by means of the APB3/MCI interfaces. In the later case the XPCS can be mapped 50 MCI or APB3 management interfaces, then the space mapping can be 80 The MCI and APB3 interfaces are supposed to be equipped with a clock
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/linux/Documentation/devicetree/bindings/hwmon/ |
H A D | baikal,bt1-pvt.yaml | 20 sensor core functionality (APB3-bus based) and exposes an additional 41 APB3-------------------------------------------------+ 61 - description: APB3 interface clock
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/linux/Documentation/devicetree/bindings/gpio/ |
H A D | nuvoton,sgpio.yaml | 17 Clock is a division of the APB3 clock.
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/linux/Documentation/devicetree/bindings/watchdog/ |
H A D | snps,dw-wdt.yaml | 49 - description: APB3 interface clock
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/linux/include/dt-bindings/mfd/ |
H A D | stm32h7-rcc.h | 58 /* APB3 */
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/linux/drivers/net/pcs/ |
H A D | pcs-xpcs-plat.c | 308 pxpcs->bus->name = "DW XPCS MCI/APB3"; in xpcs_plat_init_bus() 321 * the MDIO and MCI/APB3 IO interfaces utilized for the DW XPCS CSRs in xpcs_plat_init_bus()
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/linux/drivers/clk/thead/ |
H A D | clk-th1520-ap.c | 477 .hw.init = CLK_HW_INIT_PARENTS_HW("apb3-cpusys-pclk", 795 static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hclk, "perisys-apb3-hclk", perisys_ahb_hclk_pd,
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/linux/drivers/clk/ |
H A D | clk-npcm7xx.c | 213 #define NPCM7XX_CLK_S_APB3 "apb3"
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H A D | clk-npcm8xx.c | 203 …{ NPCM8XX_CLKDIV2, 28, 2, "apb3", &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POW…
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H A D | clk-stm32h7.c | 526 /* * APB3 peripheral */ in register_core_and_bus_clocks()
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/linux/drivers/clk/nxp/ |
H A D | clk-lpc18xx-cgu.c | 230 LPC1XX_CGU_BASE_CLK(APB3, base_common_src_ids, 0),
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/linux/drivers/gpu/drm/meson/ |
H A D | meson_dw_hdmi.c | 613 /* Enable APB3 fail on error */ in meson_dw_hdmi_init()
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/linux/drivers/hwmon/ |
H A D | bt1-pvt.c | 183 * sub-block registers space via the APB3 bus. In addition the wrapper provides
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/linux/drivers/net/ethernet/amd/xgbe/ |
H A D | xgbe-dev.c | 1228 /* The PCS registers are accessed using mmio. The underlying APB3 in xgbe_read_mmd_regs_v1() 1256 /* The PCS registers are accessed using mmio. The underlying APB3 in xgbe_write_mmd_regs_v1()
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