| /freebsd/sys/contrib/device-tree/Bindings/ata/ |
| H A D | ahci-platform.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
13 It is possible, but not required, to represent each port as a sub-node.
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
23 compatible:
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| H A D | ahci-platform.txt | 1 * AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
6 It is possible, but not required, to represent each port as a sub-node.
11 - compatible : compatible string, one of:
12 - "brcm,iproc-ahci"
13 - "hisilicon,hisi-ahci"
14 - "cavium,octeon-7130-ahci"
15 - "ibm,476gtr-ahci"
16 - "marvell,armada-380-ahci"
17 - "marvell,armada-3700-ahci"
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| H A D | rockchip,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller found in Rockchip
19 compatible:
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
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| H A D | snps,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller.
18 compatible:
20 - snps,dwc-ahci
21 - snps,spear-ahci
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| H A D | brcm,sata-brcm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SATA3 AHCI Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
14 - Florian Fainelli <f.fainelli@gmail.com>
17 - $ref: ahci-common.yaml#
20 compatible:
22 - items:
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| H A D | nvidia,tegra-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci
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| H A D | allwinner,sun8i-r40-ahci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner R40 AHCI SATA Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 compatible:
15 const: allwinner,sun8i-r40-ahci
22 - description: AHCI Bus Clock
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| H A D | brcm,sata-brcm.txt | 1 * Broadcom SATA3 AHCI Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
7 - compatible : should be one or more of
8 "brcm,bcm7216-ahci"
9 "brcm,bcm7425-ahci"
10 "brcm,bcm7445-ahci"
11 "brcm,bcm-nsp-ahci"
12 "brcm,sata3-ahci"
13 "brcm,bcm63138-ahci"
14 - reg : register mappings for AHCI and SATA_TOP_CTRL
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| H A D | allwinner,sun4i-a10-ahci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/allwinner,sun4i-a10-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 AHCI SATA Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 compatible:
15 const: allwinner,sun4i-a10-ahci
22 - description: AHCI Bus Clock
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| H A D | baikal,bt1-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
20 compatible:
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| H A D | ahci-mtk.txt | 4 - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
5 When using "mediatek,mtk-ahci" compatible strings, you
7 - "mediatek,mt7622-ahci"
8 - reg : Physical base addresses and length of register sets.
9 - interrupts : Interrupt associated with the SATA device.
10 - interrupt-names : Associated name must be: "hostc".
11 - clocks : A list of phandle and clock specifier pairs, one for each
12 entry in clock-names.
13 - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
14 - phys : A phandle and PHY specifier pair for the PHY port.
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| H A D | qcom-sata.txt | 1 * Qualcomm AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
7 - compatible : compatible list, must contain "generic-ahci"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - phys : Must contain exactly one entry as specified
11 in phy-bindings.txt
12 - phy-names : Must be "sata-phy"
14 Required properties for "qcom,ipq806x-ahci" compatible:
15 - clocks : Must contain an entry for each entry in clock-names.
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| H A D | imx-sata.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX AHCI SATA Controller
10 - Shawn Guo <shawn.guo@linaro.org>
13 The Freescale i.MX SATA controller mostly conforms to the AHCI interface
17 compatible:
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
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| H A D | imx-sata.txt | 1 * Freescale i.MX AHCI SATA Controller
3 The Freescale i.MX SATA controller mostly conforms to the AHCI interface
7 - compatible : should be one of the following:
8 - "fsl,imx53-ahci" for i.MX53 SATA controller
9 - "fsl,imx6q-ahci" for i.MX6Q SATA controller
10 - "fsl,imx6qp-ahci" for i.MX6QP SATA controller
11 - interrupts : interrupt mapping for SATA IRQ
12 - reg : registers mapping
13 - clocks : list of clock specifiers, must contain an entry for each
14 required entry in clock-names
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| H A D | apm-xgene.txt | 1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
23 - phy-names : Should contain:
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| H A D | ahci-fsl-qoriq.txt | 1 Binding for Freescale QorIQ AHCI SATA Controller
4 - reg: Physical base address and size of the controller's register area.
5 - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
7 - clocks: Input clock specifier. Refer to common clock bindings.
8 - interrupts: Interrupt specifier. Refer to interrupt binding.
11 - dma-coherent: Enable AHCI coherent DMA operation.
12 - reg-names: register area names when there are more than 1 register area.
16 compatible = "fsl,ls1021a-ahci";
20 dma-coherent;
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| H A D | ahci-da850.txt | 1 Device tree binding for the TI DA850 AHCI SATA Controller
2 ---------------------------------------------------------
5 - compatible: must be "ti,da850-ahci"
6 - reg: physical base addresses and sizes of the two register regions
8 AHCI 1.1 standard and the Power Down Control Register (PWRDN)
10 - interrupts: interrupt specifier (refer to the interrupt binding)
15 compatible = "ti,da850-ahci";
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| /freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/ |
| H A D | stingray-sata.dtsi | 4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
39 sata0: ahci@0 {
40 compatible = "brcm,iproc-ahci", "generic-ahci";
42 reg-names = "ahci";
44 #address-cells = <1>;
45 #size-cells = <0>;
48 sata0_port0: sata-port@0 {
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| /freebsd/sys/contrib/device-tree/Bindings/soc/socionext/ |
| H A D | socionext,uniphier-ahci-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC AHCI glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
14 logic handling signals to AHCI host controller inside AHCI component.
17 compatible:
19 - enum:
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | socionext,uniphier-ahci-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-ahci-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier AHCI PHY
11 AHCI controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17 compatible:
19 - socionext,uniphier-pro4-ahci-phy
20 - socionext,uniphier-pxs2-ahci-phy
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/reset/ |
| H A D | uniphier-reset.txt | 5 -----------------------------------
12 - compatible: Should be
13 "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
14 "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
15 "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
16 "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
17 "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
18 "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
19 "socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI
20 "socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI
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| H A D | socionext,uniphier-glue-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 compatible:
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
23 - socionext,uniphier-pxs2-usb3-reset
24 - socionext,uniphier-ld20-usb3-reset
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| /freebsd/share/man/man4/ |
| H A D | ahci.4 | 1 .\" Copyright (c) 2009-2013 Alexander Motin <mav@FreeBSD.org>
29 .Nm ahci
35 .Bd -ragged -offset indent
38 .Cd "device ahci"
44 .Bd -literal -offset indent
50 .Bl -ohang
51 .It Va hint.ahci. Ns Ar X Ns Va .msi
54 .Bl -tag -width 4n -offset indent -compact
62 .It Va hint.ahci. Ns Ar X Ns Va .ccc
64 Non-zero value enables CCC and defines maximum time (in ms), request can wait
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/4xx/ |
| H A D | akebono.txt | 11 - model : "ibm,akebono".
12 - compatible : "ibm,akebono" , "ibm,476gtr".
20 - compatible : should be "ibm,476gtr-sdhci","generic-sdhci".
21 - reg : should contain the SDHCI registers location and length.
22 - interrupts : should contain the SDHCI interrupt.
24 1.b) The Advanced Host Controller Interface (AHCI) SATA node
30 - compatible : should be "ibm,476gtr-ahci".
31 - reg : should contain the AHCI registers location and length.
32 - interrupts : should contain the AHCI interrupt.
41 - compatible : should be "ibm,akebono-fpga".
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| /freebsd/sys/contrib/device-tree/Bindings/mips/cavium/ |
| H A D | sata-uctl.txt | 4 and the SATA AHCI host controller (UAHC). It performs the following functions:
5 - provides interfaces for the applications to access the UAHC AHCI
7 - provides a bridge for UAHC to fetch AHCI command table entries and data
9 - posts interrupts to the CIU.
10 - contains registers that:
11 - control the behavior of the UAHC
12 - control the clock/reset generation to UAHC
13 - control endian swapping for all UAHC registers and DMA accesses
17 - compatible: "cavium,octeon-7130-sata-uctl"
21 - reg: The base address of the UCTL register bank.
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