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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FalkorHWPFFix.cpp15 #include "AArch64.h"
54 #define DEBUG_TYPE "aarch64-falkor-hwpf-fix"
224 INITIALIZE_PASS_BEGIN(FalkorHWPFFix, "aarch64-falkor-hwpf-fix-late",
227 INITIALIZE_PASS_END(FalkorHWPFFix, "aarch64-falkor-hwpf-fix-late", in INITIALIZE_PASS_DEPENDENCY()
244 case AArch64::LD1i64: in getLoadInfo()
245 case AArch64::LD2i64: in getLoadInfo()
252 case AArch64::LD1i8: in getLoadInfo()
253 case AArch64::LD1i16: in getLoadInfo()
254 case AArch64::LD1i32: in getLoadInfo()
255 case AArch64::LD2i8: in getLoadInfo()
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H A DAArch64MacroFusion.cpp1 //===- AArch64MacroFusion.cpp - AArch64 Macro Fusion ----------------------===//
9 /// \file This file contains the AArch64 implementation of the DAG scheduling
24 if (SecondMI.getOpcode() != AArch64::Bcc) in isArithmeticBccPair()
34 !(FirstMI->getOperand(0).getReg() == AArch64::XZR || in isArithmeticBccPair()
35 FirstMI->getOperand(0).getReg() == AArch64::WZR)) { in isArithmeticBccPair()
40 case AArch64::ADDSWri: in isArithmeticBccPair()
41 case AArch64::ADDSWrr: in isArithmeticBccPair()
42 case AArch64::ADDSXri: in isArithmeticBccPair()
43 case AArch64::ADDSXrr: in isArithmeticBccPair()
44 case AArch64::ANDSWri: in isArithmeticBccPair()
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H A DAArch64InstrInfo.cpp1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
67 "aarch64-tbz-offset-bits", cl::Hidden, cl::init(14),
71 "aarch64-cbz-offset-bits", cl::Hidden, cl::init(19),
75 BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19),
79 BDisplacementBits("aarch64-b-offset-bits", cl::Hidden, cl::init(26),
83 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP, in AArch64InstrInfo()
84 AArch64::CATCHRET), in AArch64InstrInfo()
97 if (Op == AArch64::INLINEASM || Op == AArch64::INLINEASM_BR) in getInstSizeInBytes()
111 // llvm/lib/Target/AArch64/AArch64InstrInfo.td (default case). in getInstSizeInBytes()
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H A DAArch64ExpandPseudoInsts.cpp45 #define AARCH64_EXPAND_PSEUDO_NAME "AArch64 pseudo instruction expansion pass"
105 INITIALIZE_PASS(AArch64ExpandPseudo, "aarch64-expand-pseudo",
134 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) { in expandMOVImm()
152 case AArch64::ORRWri: in expandMOVImm()
153 case AArch64::ORRXri: in expandMOVImm()
157 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR) in expandMOVImm()
171 case AArch64::ORRWrs: in expandMOVImm()
172 case AArch64::ORRXrs: { in expandMOVImm()
184 case AArch64::ANDXri: in expandMOVImm()
185 case AArch64::EORXri: in expandMOVImm()
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H A DAArch64SIMDInstrOpt.cpp57 #define DEBUG_TYPE "aarch64-simdinstr-opt"
63 "AArch64 SIMD instructions optimization pass"
104 RuleST2(AArch64::ST2Twov2d, AArch64::ZIP1v2i64, AArch64::ZIP2v2i64,
105 AArch64::STPQi, AArch64::FPR128RegClass),
106 RuleST2(AArch64::ST2Twov4s, AArch64::ZIP1v4i32, AArch64
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H A DAArch64DeadRegisterDefinitionsPass.cpp13 #include "AArch64.h"
28 #define DEBUG_TYPE "aarch64-dead-defs"
32 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
61 INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
79 case AArch64::LDADDB: case AArch64::LDADDH: in atomicReadDroppedOnZero()
80 case AArch64::LDADDW: case AArch64::LDADDX: in atomicReadDroppedOnZero()
81 case AArch64::LDADDLB: case AArch64::LDADDLH: in atomicReadDroppedOnZero()
82 case AArch64::LDADDLW: case AArch64::LDADDLX: in atomicReadDroppedOnZero()
83 case AArch64::LDCLRB: case AArch64::LDCLRH: in atomicReadDroppedOnZero()
84 case AArch64::LDCLRW: case AArch64::LDCLRX: in atomicReadDroppedOnZero()
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H A DAArch64PBQPRegAlloc.cpp1 //===-- AArch64PBQPRegAlloc.cpp - AArch64 specific PBQP constraints -------===//
8 // This file contains the AArch64 / Cortex-A57 specific register allocation
18 #include "AArch64.h"
30 #define DEBUG_TYPE "aarch64-pbqp"
40 case AArch64::S1: in isOdd()
41 case AArch64::S3: in isOdd()
42 case AArch64::S5: in isOdd()
43 case AArch64::S7: in isOdd()
44 case AArch64::S9: in isOdd()
45 case AArch64::S11: in isOdd()
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H A DAArch64CondBrTuning.cpp1 //===-- AArch64CondBrTuning.cpp --- Conditional branch tuning for AArch64 -===//
28 #include "AArch64.h"
43 #define DEBUG_TYPE "aarch64-cond-br-tuning"
44 #define AARCH64_CONDBR_TUNING_NAME "AArch64 Conditional Branch Tuning"
73 INITIALIZE_PASS(AArch64CondBrTuning, "aarch64-cond-br-tuning",
94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV) in convertToFlagSetting()
101 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in convertToFlagSetting()
118 case AArch64::CBZW: in convertToCondBr()
119 case AArch64::CBZX: in convertToCondBr()
122 case AArch64::CBNZW: in convertToCondBr()
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H A DAArch64AsmPrinter.cpp1 //===- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer ---------------===//
10 // of machine-dependent LLVM code to the AArch64 assembly language.
14 #include "AArch64.h"
73 "aarch64-ptrauth-auth-checks", cl::Hidden,
95 StringRef getPassName() const override { return "AArch64 Assembly Printer"; } in getPassName()
308 M.getModuleFlag("aarch64-elf-pauthabi-platform"))) in emitStartOfAsmFile()
312 M.getModuleFlag("aarch64-elf-pauthabi-version"))) in emitStartOfAsmFile()
382 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8)); in emitSled()
385 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); in emitSled()
411 MCInst MovX0Op0 = MCInstBuilder(AArch64::ORRXrs) in LowerPATCHABLE_EVENT_CALL()
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H A DAArch64LoadStoreOptimizer.cpp1 //===- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -------===//
56 #define DEBUG_TYPE "aarch64-ldst-opt"
72 static cl::opt<unsigned> LdStLimit("aarch64-load-store-scan-limit",
77 static cl::opt<unsigned> UpdateLimit("aarch64-update-scan-limit", cl::init(100),
81 static cl::opt<bool> EnableRenaming("aarch64-load-store-renaming",
84 #define AARCH64_LOAD_STORE_OPT_NAME "AArch64 load / store optimization pass"
220 INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
227 case AArch64::STRBBui: in isNarrowStore()
228 case AArch64::STURBBi: in isNarrowStore()
229 case AArch64::STRHHui: in isNarrowStore()
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H A DAArch64ISelDAGToDAG.cpp1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
9 // This file defines an instruction selector for the AArch64 target.
31 #define DEBUG_TYPE "aarch64-isel"
32 #define PASS_NAME "AArch64 Instruction Selection"
35 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
767 NewShiftOp = VT == MVT::i64 ? AArch64::UBFMXri : AArch64::UBFMWri; in SelectShiftedRegisterFromAnd()
786 NewShiftOp = VT == MVT::i64 ? AArch64::UBFMXri : AArch64::UBFMWri; in SelectShiftedRegisterFromAnd()
788 NewShiftOp = VT == MVT::i64 ? AArch64::SBFMXri : AArch64::SBFMWri; in SelectShiftedRegisterFromAnd()
915 return CurDAG->getTargetExtractSubreg(AArch64::sub_32, dl, MVT::i32, N); in narrowIfNeeded()
977 // AArch64 mandates that the RHS of the operation must use the smallest in SelectArithExtendedRegister()
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H A DAArch64CallingConvention.cpp1 //=== AArch64CallingConvention.cpp - AArch64 CC impl ------------*- C++ -*-===//
9 // This file contains the table-generated and custom routines for the AArch64
15 #include "AArch64.h"
23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
24 AArch64::X3, AArch64::X4, AArch64::X5,
25 AArch64::X6, AArch64::X7};
26 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
27 AArch64::H3, AArch64::H4, AArch64::H5,
28 AArch64::H6, AArch64::H7};
29 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
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H A DAArch64FastISel.cpp1 //===- AArch6464FastISel.cpp - AArch64 FastISel implementation ------------===//
9 // This file defines the AArch64-specific support for the FastISel class. Some
15 #include "AArch64.h"
362 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca()
363 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::ADDXri), in fastMaterializeAlloca()
382 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
383 : &AArch64::GPR32RegClass; in materializeInt()
384 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt()
407 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi; in materializeFP()
413 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP()
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H A DAArch64StackTaggingPreRA.cpp1 //===-- AArch64StackTaggingPreRA.cpp --- Stack Tagging for AArch64 -----===//
10 #include "AArch64.h"
33 #define DEBUG_TYPE "aarch64-stack-tagging-pre-ra"
80 return "AArch64 Stack Tagging PreRA"; in getPassName()
92 INITIALIZE_PASS_BEGIN(AArch64StackTaggingPreRA, "aarch64-stack-tagging-pre-ra",
93 "AArch64 Stack Tagging PreRA Pass", false, false)
94 INITIALIZE_PASS_END(AArch64StackTaggingPreRA, "aarch64-stack-tagging-pre-ra",
95 "AArch64 Stack Tagging PreRA Pass", false, false)
103 case AArch64::LDRBBui: in isUncheckedLoadOrStoreOpcode()
104 case AArch64 in isUncheckedLoadOrStoreOpcode()
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H A DAArch64RegisterInfo.cpp1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
9 // This file contains the AArch64 implementation of the TargetRegisterInfo
43 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) { in AArch64RegisterInfo()
54 if (AArch64::PPRRegClass.contains(Reg)) in regNeedsCFI()
57 if (AArch64::ZPRRegClass.contains(Reg)) { in regNeedsCFI()
58 RegToUseForCFI = getSubReg(Reg, AArch64::dsub); in regNeedsCFI()
219 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) { in UpdateCustomCalleeSavedRegs()
221 UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i)); in UpdateCustomCalleeSavedRegs()
233 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub) in getSubClassWithSubReg()
234 return &AArch64::FPR32RegClass; in getSubClassWithSubReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
10 // the AArch64 target useful for the compiler back-end and the MC libraries.
21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
32 case AArch64::X0: return AArch64::W0; in getWRegFromXReg()
33 case AArch64::X1: return AArch64::W1; in getWRegFromXReg()
34 case AArch64::X2: return AArch64::W2; in getWRegFromXReg()
35 case AArch64::X3: return AArch64::W3; in getWRegFromXReg()
36 case AArch64::X4: return AArch64::W4; in getWRegFromXReg()
37 case AArch64::X5: return AArch64::W5; in getWRegFromXReg()
38 case AArch64::X6: return AArch64::W6; in getWRegFromXReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
34 #define DEBUG_TYPE "aarch64-disassembler"
256 case AArch64::MPRRegClassID: in getInstruction()
257 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA)); in getInstruction()
259 case AArch64::MPR8RegClassID: in getInstruction()
260 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0)); in getInstruction()
262 case AArch64::ZTRRegClassID: in getInstruction()
263 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0)); in getInstruction()
267 AArch64::OPERAND_IMPLICIT_IMM_0) { in getInstruction()
272 if (MI.getOpcode() == AArch64::LDR_ZA || in getInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
9 // This file provides AArch64 specific target descriptions.
55 CPU = AArch64::resolveCPUAlias(CPU); in createAArch64MCSubtargetInfo()
75 {codeview::RegisterId::ARM64_W0, AArch64::W0}, in initLLVMToCVRegMapping()
76 {codeview::RegisterId::ARM64_W1, AArch64::W1}, in initLLVMToCVRegMapping()
77 {codeview::RegisterId::ARM64_W2, AArch64::W2}, in initLLVMToCVRegMapping()
78 {codeview::RegisterId::ARM64_W3, AArch64::W3}, in initLLVMToCVRegMapping()
79 {codeview::RegisterId::ARM64_W4, AArch64::W4}, in initLLVMToCVRegMapping()
80 {codeview::RegisterId::ARM64_W5, AArch64::W5}, in initLLVMToCVRegMapping()
81 {codeview::RegisterId::ARM64_W6, AArch64::W6}, in initLLVMToCVRegMapping()
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H A DAArch64InstPrinter.cpp1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
9 // This class prints an AArch64 MCInst to a .s file.
82 if (Opcode == AArch64::SYSxt) in printInst()
88 if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) in printInst()
95 if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) { in printInst()
101 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || in printInst()
102 Opcode == AArch64 in printInst()
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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A DELF_aarch64.cpp1 //===----- ELF_aarch64.cpp - JIT linker implementation for ELF/aarch64 ----===//
9 // ELF/aarch64 jit-link implementation.
16 #include "llvm/ExecutionEngine/JITLink/aarch64.h"
43 return aarch64::applyFixup(G, B, E); in applyFixup()
81 using namespace aarch64; in getRelocationKind()
139 "Unsupported aarch64 relocation:" + formatv("{0:d}: ", Type) + in getRelocationKind()
194 Kind = aarch64::Branch26PCRel; in addSingleRelocation()
199 if (!aarch64::isLDRLiteral(Instr)) in addSingleRelocation()
203 Kind = aarch64::LDRLiteral19; in addSingleRelocation()
208 if (!aarch64::isADR(Instr)) in addSingleRelocation()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
97 case AArch64::MOVPRFX_ZZ: in CreateFromInst()
101 case AArch64::MOVPRFX_ZPmZ_B: in CreateFromInst()
102 case AArch64::MOVPRFX_ZPmZ_H: in CreateFromInst()
103 case AArch64::MOVPRFX_ZPmZ_S: in CreateFromInst()
104 case AArch64::MOVPRFX_ZPmZ_D: in CreateFromInst()
107 Prefix.ElementSize = TSFlags & AArch64::ElementSizeMask; in CreateFromInst()
108 assert(Prefix.ElementSize != AArch64::ElementSizeNone && in CreateFromInst()
113 case AArch64::MOVPRFX_ZPzZ_B: in CreateFromInst()
114 case AArch64::MOVPRFX_ZPzZ_H: in CreateFromInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp14 #include "AArch64.h"
27 #define DEBUG_TYPE "aarch64-post-select-optimize"
39 return "AArch64 Post Select Optimizer"; in getPassName()
71 case AArch64::SUBSXrr: in getNonFlagSettingVariant()
72 return AArch64::SUBXrr; in getNonFlagSettingVariant()
73 case AArch64::SUBSWrr: in getNonFlagSettingVariant()
74 return AArch64::SUBWrr; in getNonFlagSettingVariant()
75 case AArch64::SUBSXrs: in getNonFlagSettingVariant()
76 return AArch64::SUBXrs; in getNonFlagSettingVariant()
77 case AArch64::SUBSWrs: in getNonFlagSettingVariant()
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H A DAArch64InstructionSelector.cpp10 /// AArch64.
52 #define DEBUG_TYPE "aarch64-isel"
209 /// @llvm.aarch64.neon.ld2.*, @llvm.aarch64.neon.ld4.*, etc.
274 /// {{AArch64::ADDXri, AArch64::ADDWri},
275 /// {AArch64::ADDXrs, AArch64::ADDWrs},
276 /// {AArch64::ADDXrr, AArch64::ADDWrr},
277 /// {AArch64::SUBXri, AArch64::SUBWri},
278 /// {AArch64::ADDXrx, AArch64::ADDWrx}}};
573 if (RB.getID() == AArch64::GPRRegBankID) { in getRegClassForTypeOnBank()
575 return GetAllRegSet ? &AArch64::GPR32allRegClass in getRegClassForTypeOnBank()
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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/cpu_model/
H A Daarch64.c1 //===-- cpu_model/aarch64.c - Support for __cpu_model builtin ----*- C -*-===//
11 // AArch64.
15 #include "aarch64.h"
18 #error This file is intended only for aarch64-based targets
40 #include "aarch64/hwcap.inc"
41 #include "aarch64/lse_atomics/freebsd.inc"
43 #include "aarch64/hwcap.inc"
44 #include "aarch64/lse_atomics/fuchsia.inc"
46 #include "aarch64/hwcap.inc"
47 #include "aarch64/lse_atomics/android.inc"
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DAArch64TargetParser.cpp1 //===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
9 // This file implements a target parser to recognise AArch64 hardware features
36 const AArch64::ArchInfo *AArch64::getArchForCpu(StringRef CPU) { in getArchForCpu()
44 std::optional<AArch64::ArchInfo> AArch64::ArchInfo::findBySubArch(StringRef SubArch) { in findBySubArch()
45 for (const auto *A : AArch64::ArchInfos) in findBySubArch()
51 uint64_t AArch64::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) { in getCpuSupportsMask()
60 bool AArch64::getExtensionFeatures( in getExtensionFeatures()
61 const AArch64::ExtensionBitset &InputExts, in getExtensionFeatures()
71 StringRef AArch64::resolveCPUAlias(StringRef Name) { in resolveCPUAlias()
78 StringRef AArch64::getArchExtFeature(StringRef ArchExt) { in getArchExtFeature()
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