Lines Matching full:aarch64
1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
9 // This class prints an AArch64 MCInst to a .s file.
82 if (Opcode == AArch64::SYSxt)
88 if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR)
95 if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) {
101 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
102 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
108 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
109 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
153 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
156 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
160 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
163 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
166 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
169 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
212 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
218 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
219 (ImmR == 0 || ImmS < ImmR) && STI.hasFeature(AArch64::HasV8_2aOps)) {
221 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
235 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
269 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
270 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
272 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
287 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
322 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
324 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
329 Opcode == AArch64::MOVZXi ? 64 : 32)) {
335 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
337 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
349 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
350 (MI->getOperand(1).getReg() == AArch64::XZR ||
351 MI->getOperand(1).getReg() == AArch64::WZR) &&
353 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
362 if (Opcode == AArch64::SPACE) {
371 if (Opcode == AArch64::TSB) {
382 (MI->getOperand(0).getReg() == AArch64::XZR ||
383 MI->getOperand(0).getReg() == AArch64::WZR)) {
391 case AArch64::TBXv8i8One:
392 case AArch64::TBXv8i8Two:
393 case AArch64::TBXv8i8Three:
394 case AArch64::TBXv8i8Four:
398 case AArch64::TBLv8i8One:
399 case AArch64::TBLv8i8Two:
400 case AArch64::TBLv8i8Three:
401 case AArch64::TBLv8i8Four:
405 case AArch64::TBXv16i8One:
406 case AArch64::TBXv16i8Two:
407 case AArch64::TBXv16i8Three:
408 case AArch64::TBXv16i8Four:
412 case AArch64::TBLv16i8One:
413 case AArch64::TBLv16i8Two:
414 case AArch64::TBLv16i8Three:
415 case AArch64::TBLv16i8Four:
434 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
435 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
436 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
437 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
438 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
439 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
440 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
441 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
442 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
443 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
444 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
445 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
446 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
447 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
448 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
449 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
450 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
451 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
452 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
453 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
454 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
455 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
456 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
457 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
458 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
459 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
460 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
461 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
462 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
463 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
464 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
465 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
466 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
467 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
468 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
469 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
470 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
471 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
472 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
473 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
474 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
475 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
476 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
477 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
478 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
479 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
480 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
481 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
482 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
483 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
484 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
485 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
486 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
487 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
488 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
489 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
490 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
491 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
492 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
493 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
494 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
495 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
496 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
497 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
498 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
499 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
500 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
501 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
502 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
503 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
504 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
505 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
506 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
507 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
508 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
509 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
510 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
511 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
512 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
513 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
514 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
515 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
516 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
517 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
518 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
519 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
520 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
521 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
522 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
523 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
524 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
525 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
526 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
527 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
528 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
529 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
530 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
531 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
532 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
533 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
534 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
535 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
536 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
537 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
538 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
539 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
540 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
541 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
542 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
543 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
544 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
545 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
546 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
547 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
548 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
549 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
550 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
551 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
552 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
553 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
554 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
555 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
556 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
557 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
558 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
559 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
560 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
561 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
562 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
563 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
564 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
565 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
566 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
567 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
568 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
569 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
570 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
571 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
572 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
573 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
574 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
575 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
576 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
577 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
578 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
579 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
580 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
581 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
582 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
583 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
584 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
585 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
586 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
587 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
588 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
589 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
590 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
591 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
592 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
593 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
594 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
595 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
596 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
597 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
598 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
599 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
600 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
601 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
602 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
603 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
604 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
605 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
606 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
607 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
608 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
609 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
610 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
611 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
612 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
613 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
614 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
615 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
616 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
617 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
618 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
619 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
620 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
621 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
622 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
623 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
624 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
625 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
626 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
627 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
628 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
629 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
630 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
631 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
632 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
633 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
634 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
635 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
636 { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
637 { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
638 { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
639 { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
640 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
641 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
642 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
643 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
644 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
645 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
646 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
647 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
648 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
649 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
650 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
651 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
652 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
653 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
654 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
655 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
656 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
657 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
658 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
659 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
660 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
661 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
662 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
663 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
664 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
665 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
666 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
667 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
668 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
669 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
670 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
671 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
672 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
673 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
674 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
675 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
676 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
677 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
678 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
679 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
680 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
681 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
682 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
683 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
684 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
685 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
686 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
687 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
688 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
689 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
690 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
691 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
692 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
693 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
694 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
695 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
696 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
697 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
698 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
699 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
700 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
701 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
702 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
703 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
704 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
705 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
706 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
707 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
708 { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
709 { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
710 { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
711 { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
712 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
713 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
714 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
715 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
716 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
717 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
718 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
719 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
720 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
721 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
722 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
723 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
724 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
725 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
726 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
727 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
728 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
729 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
730 { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
731 { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
732 { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
733 { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
734 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
735 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
736 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
737 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
738 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
739 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
740 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
741 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
742 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
743 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
744 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
745 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
746 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
747 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
748 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
749 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
750 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
751 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
752 { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
753 { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
754 { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
755 { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
756 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
757 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
758 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
759 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
760 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
761 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
762 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
763 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
764 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
765 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
766 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
767 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
768 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
769 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
770 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
771 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
772 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
773 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
794 printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
801 printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
826 if (Reg != AArch64::XZR) {
854 assert(((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) &&
866 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm))
867 Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32,
868 &MRI.getRegClass(AArch64::GPR64RegClassID));
876 unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0;
902 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
941 Op2Val == 6 ? AArch64::FeatureSPECRES2 : AArch64::FeaturePredRes;
942 if (!(STI.hasFeature(AArch64::FeatureAll) || STI.hasFeature(Requires)))
1022 assert((Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) &&
1048 if (!STI.hasFeature(AArch64::FeatureXS))
1069 if (MI->getOperand(4).getReg() == AArch64::XZR)
1188 if (Reg == AArch64::XZR)
1202 printRegName(O, Reg, AArch64::vreg);
1285 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1287 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1351 if (Reg < AArch64::PN0 || Reg > AArch64::PN15)
1353 O << "pn" << Reg - AArch64::PN0;
1512 case AArch64::Q0: Reg = AArch64::Q1; break;
1513 case AArch64::Q1: Reg = AArch64::Q2; break;
1514 case AArch64::Q2: Reg = AArch64::Q3; break;
1515 case AArch64::Q3: Reg = AArch64::Q4; break;
1516 case AArch64::Q4: Reg = AArch64::Q5; break;
1517 case AArch64::Q5: Reg = AArch64::Q6; break;
1518 case AArch64::Q6: Reg = AArch64::Q7; break;
1519 case AArch64::Q7: Reg = AArch64::Q8; break;
1520 case AArch64::Q8: Reg = AArch64::Q9; break;
1521 case AArch64::Q9: Reg = AArch64::Q10; break;
1522 case AArch64::Q10: Reg = AArch64::Q11; break;
1523 case AArch64::Q11: Reg = AArch64::Q12; break;
1524 case AArch64::Q12: Reg = AArch64::Q13; break;
1525 case AArch64::Q13: Reg = AArch64::Q14; break;
1526 case AArch64::Q14: Reg = AArch64::Q15; break;
1527 case AArch64::Q15: Reg = AArch64::Q16; break;
1528 case AArch64::Q16: Reg = AArch64::Q17; break;
1529 case AArch64::Q17: Reg = AArch64::Q18; break;
1530 case AArch64::Q18: Reg = AArch64::Q19; break;
1531 case AArch64::Q19: Reg = AArch64::Q20; break;
1532 case AArch64::Q20: Reg = AArch64::Q21; break;
1533 case AArch64::Q21: Reg = AArch64::Q22; break;
1534 case AArch64::Q22: Reg = AArch64::Q23; break;
1535 case AArch64::Q23: Reg = AArch64::Q24; break;
1536 case AArch64::Q24: Reg = AArch64::Q25; break;
1537 case AArch64::Q25: Reg = AArch64::Q26; break;
1538 case AArch64::Q26: Reg = AArch64::Q27; break;
1539 case AArch64::Q27: Reg = AArch64::Q28; break;
1540 case AArch64::Q28: Reg = AArch64::Q29; break;
1541 case AArch64::Q29: Reg = AArch64::Q30; break;
1542 case AArch64::Q30: Reg = AArch64::Q31; break;
1544 case AArch64::Q31:
1545 Reg = AArch64::Q0;
1547 case AArch64::Z0: Reg = AArch64::Z1; break;
1548 case AArch64::Z1: Reg = AArch64::Z2; break;
1549 case AArch64::Z2: Reg = AArch64::Z3; break;
1550 case AArch64::Z3: Reg = AArch64::Z4; break;
1551 case AArch64::Z4: Reg = AArch64::Z5; break;
1552 case AArch64::Z5: Reg = AArch64::Z6; break;
1553 case AArch64::Z6: Reg = AArch64::Z7; break;
1554 case AArch64::Z7: Reg = AArch64::Z8; break;
1555 case AArch64::Z8: Reg = AArch64::Z9; break;
1556 case AArch64::Z9: Reg = AArch64::Z10; break;
1557 case AArch64::Z10: Reg = AArch64::Z11; break;
1558 case AArch64::Z11: Reg = AArch64::Z12; break;
1559 case AArch64::Z12: Reg = AArch64::Z13; break;
1560 case AArch64::Z13: Reg = AArch64::Z14; break;
1561 case AArch64::Z14: Reg = AArch64::Z15; break;
1562 case AArch64::Z15: Reg = AArch64::Z16; break;
1563 case AArch64::Z16: Reg = AArch64::Z17; break;
1564 case AArch64::Z17: Reg = AArch64::Z18; break;
1565 case AArch64::Z18: Reg = AArch64::Z19; break;
1566 case AArch64::Z19: Reg = AArch64::Z20; break;
1567 case AArch64::Z20: Reg = AArch64::Z21; break;
1568 case AArch64::Z21: Reg = AArch64::Z22; break;
1569 case AArch64::Z22: Reg = AArch64::Z23; break;
1570 case AArch64::Z23: Reg = AArch64::Z24; break;
1571 case AArch64::Z24: Reg = AArch64::Z25; break;
1572 case AArch64::Z25: Reg = AArch64::Z26; break;
1573 case AArch64::Z26: Reg = AArch64::Z27; break;
1574 case AArch64::Z27: Reg = AArch64::Z28; break;
1575 case AArch64::Z28: Reg = AArch64::Z29; break;
1576 case AArch64::Z29: Reg = AArch64::Z30; break;
1577 case AArch64::Z30: Reg = AArch64::Z31; break;
1579 case AArch64::Z31:
1580 Reg = AArch64::Z0;
1582 case AArch64::P0: Reg = AArch64::P1; break;
1583 case AArch64::P1: Reg = AArch64::P2; break;
1584 case AArch64::P2: Reg = AArch64::P3; break;
1585 case AArch64::P3: Reg = AArch64::P4; break;
1586 case AArch64::P4: Reg = AArch64::P5; break;
1587 case AArch64::P5: Reg = AArch64::P6; break;
1588 case AArch64::P6: Reg = AArch64::P7; break;
1589 case AArch64::P7: Reg = AArch64::P8; break;
1590 case AArch64::P8: Reg = AArch64::P9; break;
1591 case AArch64::P9: Reg = AArch64::P10; break;
1592 case AArch64::P10: Reg = AArch64::P11; break;
1593 case AArch64::P11: Reg = AArch64::P12; break;
1594 case AArch64::P12: Reg = AArch64::P13; break;
1595 case AArch64::P13: Reg = AArch64::P14; break;
1596 case AArch64::P14: Reg = AArch64::P15; break;
1598 case AArch64::P15: Reg = AArch64::P0; break;
1613 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1614 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1640 printRegName(O, AArch64::ZAD0 + I);
1659 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1660 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1661 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) ||
1662 MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) ||
1663 MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
1665 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1666 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
1667 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1669 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1670 MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1671 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) ||
1672 MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
1676 if (MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
1678 else if (MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
1682 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1684 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1686 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
1688 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0))
1693 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1695 MRI.getRegClass(AArch64::FPR128RegClassID);
1696 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1699 if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1700 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) &&
1718 if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1719 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg))
1722 printRegName(O, Reg, AArch64::vreg);
1809 if (MI->getOpcode() == AArch64::ADRP) {
1832 if (Opcode == AArch64::ISB) {
1835 } else if (Opcode == AArch64::TSB) {
1852 assert(MI->getOpcode() == AArch64::DSBnXS);
2085 case 8: Base = AArch64::B0; break;
2086 case 16: Base = AArch64::H0; break;
2087 case 32: Base = AArch64::S0; break;
2088 case 64: Base = AArch64::D0; break;
2089 case 128: Base = AArch64::Q0; break;
2094 printRegName(O, Reg - AArch64::Z0 + Base);
2119 printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0));
2126 assert(Reg == AArch64::XZR &&