Lines Matching full:aarch64
45 #define AARCH64_EXPAND_PSEUDO_NAME "AArch64 pseudo instruction expansion pass"
105 INITIALIZE_PASS(AArch64ExpandPseudo, "aarch64-expand-pseudo",
134 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) { in expandMOVImm()
152 case AArch64::ORRWri: in expandMOVImm()
153 case AArch64::ORRXri: in expandMOVImm()
157 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR) in expandMOVImm()
171 case AArch64::ORRWrs: in expandMOVImm()
172 case AArch64::ORRXrs: { in expandMOVImm()
184 case AArch64::ANDXri: in expandMOVImm()
185 case AArch64::EORXri: in expandMOVImm()
189 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR) in expandMOVImm()
203 case AArch64::MOVNWi: in expandMOVImm()
204 case AArch64::MOVNXi: in expandMOVImm()
205 case AArch64::MOVZWi: in expandMOVImm()
206 case AArch64::MOVZXi: { in expandMOVImm()
215 case AArch64::MOVKWi: in expandMOVImm()
216 case AArch64::MOVKXi: { in expandMOVImm()
266 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::MOVZWi), StatusReg) in expandCMP_SWAP()
274 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::Bcc)) in expandCMP_SWAP()
277 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill); in expandCMP_SWAP()
287 BuildMI(StoreBB, MIMD, TII->get(AArch64::CBNZW)) in expandCMP_SWAP()
336 case AArch64::CMP_SWAP_128_MONOTONIC: in expandCMP_SWAP_128()
337 LdxpOp = AArch64::LDXPX; in expandCMP_SWAP_128()
338 StxpOp = AArch64::STXPX; in expandCMP_SWAP_128()
340 case AArch64::CMP_SWAP_128_RELEASE: in expandCMP_SWAP_128()
341 LdxpOp = AArch64::LDXPX; in expandCMP_SWAP_128()
342 StxpOp = AArch64::STLXPX; in expandCMP_SWAP_128()
344 case AArch64::CMP_SWAP_128_ACQUIRE: in expandCMP_SWAP_128()
345 LdxpOp = AArch64::LDAXPX; in expandCMP_SWAP_128()
346 StxpOp = AArch64::STXPX; in expandCMP_SWAP_128()
348 case AArch64::CMP_SWAP_128: in expandCMP_SWAP_128()
349 LdxpOp = AArch64::LDAXPX; in expandCMP_SWAP_128()
350 StxpOp = AArch64::STLXPX; in expandCMP_SWAP_128()
376 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::SUBSXrs), AArch64::XZR) in expandCMP_SWAP_128()
380 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CSINCWr), StatusReg) in expandCMP_SWAP_128()
381 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
382 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
384 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::SUBSXrs), AArch64::XZR) in expandCMP_SWAP_128()
388 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CSINCWr), StatusReg) in expandCMP_SWAP_128()
392 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CBNZW)) in expandCMP_SWAP_128()
405 BuildMI(StoreBB, MIMD, TII->get(AArch64::CBNZW)) in expandCMP_SWAP_128()
408 BuildMI(StoreBB, MIMD, TII->get(AArch64::B)).addMBB(DoneBB); in expandCMP_SWAP_128()
419 BuildMI(FailBB, MIMD, TII->get(AArch64::CBNZW)) in expandCMP_SWAP_128()
493 unsigned Opcode = AArch64::getSVEPseudoMap(MI.getOpcode()); in expand_DestructiveOp()
494 uint64_t DType = TII->get(Opcode).TSFlags & AArch64::DestructiveInstTypeMask; in expand_DestructiveOp()
495 uint64_t FalseLanes = MI.getDesc().TSFlags & AArch64::FalseLanesMask; in expand_DestructiveOp()
496 bool FalseZero = FalseLanes == AArch64::FalseLanesZero; in expand_DestructiveOp()
503 case AArch64::DestructiveBinaryComm: in expand_DestructiveOp()
504 case AArch64::DestructiveBinaryCommWithRev: in expand_DestructiveOp()
512 case AArch64::DestructiveBinary: in expand_DestructiveOp()
513 case AArch64::DestructiveBinaryImm: in expand_DestructiveOp()
516 case AArch64::DestructiveUnaryPassthru: in expand_DestructiveOp()
519 case AArch64::DestructiveTernaryCommWithRev: in expand_DestructiveOp()
540 case AArch64::DestructiveBinary: in expand_DestructiveOp()
543 case AArch64::DestructiveBinaryComm: in expand_DestructiveOp()
544 case AArch64::DestructiveBinaryCommWithRev: in expand_DestructiveOp()
549 case AArch64::DestructiveUnaryPassthru: in expand_DestructiveOp()
550 case AArch64::DestructiveBinaryImm: in expand_DestructiveOp()
553 case AArch64::DestructiveTernaryCommWithRev: in expand_DestructiveOp()
565 if ((NewOpcode = AArch64::getSVERevInstr(Opcode)) != -1) in expand_DestructiveOp()
568 else if ((NewOpcode = AArch64::getSVENonRevInstr(Opcode)) != -1) in expand_DestructiveOp()
576 case AArch64::ElementSizeNone: in expand_DestructiveOp()
577 case AArch64::ElementSizeB: in expand_DestructiveOp()
578 MovPrfx = AArch64::MOVPRFX_ZZ; in expand_DestructiveOp()
579 LSLZero = AArch64::LSL_ZPmI_B; in expand_DestructiveOp()
580 MovPrfxZero = AArch64::MOVPRFX_ZPzZ_B; in expand_DestructiveOp()
582 case AArch64::ElementSizeH: in expand_DestructiveOp()
583 MovPrfx = AArch64::MOVPRFX_ZZ; in expand_DestructiveOp()
584 LSLZero = AArch64::LSL_ZPmI_H; in expand_DestructiveOp()
585 MovPrfxZero = AArch64::MOVPRFX_ZPzZ_H; in expand_DestructiveOp()
587 case AArch64::ElementSizeS: in expand_DestructiveOp()
588 MovPrfx = AArch64::MOVPRFX_ZZ; in expand_DestructiveOp()
589 LSLZero = AArch64::LSL_ZPmI_S; in expand_DestructiveOp()
590 MovPrfxZero = AArch64::MOVPRFX_ZPzZ_S; in expand_DestructiveOp()
592 case AArch64::ElementSizeD: in expand_DestructiveOp()
593 MovPrfx = AArch64::MOVPRFX_ZZ; in expand_DestructiveOp()
594 LSLZero = AArch64::LSL_ZPmI_D; in expand_DestructiveOp()
595 MovPrfxZero = AArch64::MOVPRFX_ZPzZ_D; in expand_DestructiveOp()
608 assert((DOPRegIsUnique || DType == AArch64::DestructiveBinary || in expand_DestructiveOp()
609 DType == AArch64::DestructiveBinaryComm || in expand_DestructiveOp()
610 DType == AArch64::DestructiveBinaryCommWithRev) && in expand_DestructiveOp()
612 assert(ElementSize != AArch64::ElementSizeNone && in expand_DestructiveOp()
627 if ((DType == AArch64::DestructiveBinary || in expand_DestructiveOp()
628 DType == AArch64::DestructiveBinaryComm || in expand_DestructiveOp()
629 DType == AArch64::DestructiveBinaryCommWithRev) && in expand_DestructiveOp()
652 case AArch64::DestructiveUnaryPassthru: in expand_DestructiveOp()
657 case AArch64::DestructiveBinary: in expand_DestructiveOp()
658 case AArch64::DestructiveBinaryImm: in expand_DestructiveOp()
659 case AArch64::DestructiveBinaryComm: in expand_DestructiveOp()
660 case AArch64::DestructiveBinaryCommWithRev: in expand_DestructiveOp()
665 case AArch64::DestructiveTernaryCommWithRev: in expand_DestructiveOp()
693 bool ZeroData = MI.getOpcode() == AArch64::STZGloop_wback; in expandSetTagLoop()
695 ZeroData ? AArch64::STZGPostIndex : AArch64::STGPostIndex; in expandSetTagLoop()
697 ZeroData ? AArch64::STZ2GPostIndex : AArch64::ST2GPostIndex; in expandSetTagLoop()
709 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVi64imm), SizeReg) in expandSetTagLoop()
726 BuildMI(LoopBB, DL, TII->get(AArch64::SUBSXri)) in expandSetTagLoop()
731 BuildMI(LoopBB, DL, TII->get(AArch64::Bcc)) in expandSetTagLoop()
734 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill); in expandSetTagLoop()
763 assert((Opc == AArch64::LDR_ZXI || Opc == AArch64::STR_ZXI || in expandSVESpillFill()
764 Opc == AArch64::LDR_PXI || Opc == AArch64::STR_PXI) && in expandSVESpillFill()
766 unsigned RState = (Opc == AArch64::LDR_ZXI || Opc == AArch64::LDR_PXI) in expandSVESpillFill()
769 unsigned sub0 = (Opc == AArch64::LDR_ZXI || Opc == AArch64::STR_ZXI) in expandSVESpillFill()
770 ? AArch64::zsub0 in expandSVESpillFill()
771 : AArch64::psub0; in expandSVESpillFill()
828 unsigned Opc = CallTarget.isGlobal() ? AArch64::BL : AArch64::BLR; in createCall()
848 if (MI.getOpcode() == AArch64::BLRA_RVMARKER) { in expandCALL_RVMARKER()
861 OriginalCall = createCallWithOps(MBB, MBBI, TII, AArch64::BLRA, Ops, in expandCALL_RVMARKER()
864 assert(MI.getOpcode() == AArch64::BLR_RVMARKER && "unknown rvmarker MI"); in expandCALL_RVMARKER()
870 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXrs)) in expandCALL_RVMARKER()
871 .addReg(AArch64::FP, RegState::Define) in expandCALL_RVMARKER()
872 .addReg(AArch64::XZR) in expandCALL_RVMARKER()
873 .addReg(AArch64::FP) in expandCALL_RVMARKER()
876 auto *RVCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::BL)) in expandCALL_RVMARKER()
904 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::HINT)) in expandCALL_BTI()
926 BuildMI(MBB, MBBI, DL, TII->get(AArch64::STRXui)) in expandStoreSwiftAsyncContext()
942 unsigned Opc = Offset >= 0 ? AArch64::ADDXri : AArch64::SUBXri; in expandStoreSwiftAsyncContext()
943 BuildMI(MBB, MBBI, DL, TII->get(Opc), AArch64::X16) in expandStoreSwiftAsyncContext()
948 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVKXi), AArch64::X16) in expandStoreSwiftAsyncContext()
949 .addUse(AArch64::X16) in expandStoreSwiftAsyncContext()
955 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ORRXrs), AArch64::X17) in expandStoreSwiftAsyncContext()
956 .addUse(AArch64::XZR) in expandStoreSwiftAsyncContext()
960 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACDB), AArch64::X17) in expandStoreSwiftAsyncContext()
961 .addUse(AArch64::X17) in expandStoreSwiftAsyncContext()
962 .addUse(AArch64::X16) in expandStoreSwiftAsyncContext()
964 BuildMI(MBB, MBBI, DL, TII->get(AArch64::STRXui)) in expandStoreSwiftAsyncContext()
965 .addUse(AArch64::X17) in expandStoreSwiftAsyncContext()
985 MachineInstrBuilder Cbz = BuildMI(MBB, MBBI, DL, TII->get(AArch64::CBZX)) in expandRestoreZA()
1000 BuildMI(&MBB, DL, TII->get(AArch64::B)) in expandRestoreZA()
1006 BuildMI(*SMBB, SMBB->end(), DL, TII->get(AArch64::BL)); in expandRestoreZA()
1010 BuildMI(SMBB, DL, TII->get(AArch64::B)).addMBB(EndBB); in expandRestoreZA()
1075 Opc = AArch64::TBNZW; in expandCondSMToggle()
1078 Opc = AArch64::TBZW; in expandCondSMToggle()
1083 unsigned SMReg32 = TRI->getSubReg(PStateSM, AArch64::sub_32); in expandCondSMToggle()
1099 BuildMI(&MBB, DL, TII->get(AArch64::B)) in expandCondSMToggle()
1105 TII->get(AArch64::MSRpstatesvcrImm1)); in expandCondSMToggle()
1114 BuildMI(SMBB, DL, TII->get(AArch64::B)).addMBB(EndBB); in expandCondSMToggle()
1156 int OrigInstr = AArch64::getSVEPseudoMap(MI.getOpcode()); in expandMI()
1159 if ((Orig.TSFlags & AArch64::DestructiveInstTypeMask) != in expandMI()
1160 AArch64::NotDestructive) { in expandMI()
1169 case AArch64::BSPv8i8: in expandMI()
1170 case AArch64::BSPv16i8: { in expandMI()
1175 TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BITv8i8 in expandMI()
1176 : AArch64::BITv16i8)) in expandMI()
1184 TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BIFv8i8 in expandMI()
1185 : AArch64::BIFv16i8)) in expandMI()
1194 TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8 in expandMI()
1195 : AArch64::BSLv16i8)) in expandMI()
1202 TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::ORRv8i8 in expandMI()
1203 : AArch64::ORRv16i8)) in expandMI()
1210 TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8 in expandMI()
1211 : AArch64::BSLv16i8)) in expandMI()
1224 case AArch64::ADDWrr: in expandMI()
1225 case AArch64::SUBWrr: in expandMI()
1226 case AArch64::ADDXrr: in expandMI()
1227 case AArch64::SUBXrr: in expandMI()
1228 case AArch64::ADDSWrr: in expandMI()
1229 case AArch64::SUBSWrr: in expandMI()
1230 case AArch64::ADDSXrr: in expandMI()
1231 case AArch64::SUBSXrr: in expandMI()
1232 case AArch64::ANDWrr: in expandMI()
1233 case AArch64::ANDXrr: in expandMI()
1234 case AArch64::BICWrr: in expandMI()
1235 case AArch64::BICXrr: in expandMI()
1236 case AArch64::ANDSWrr: in expandMI()
1237 case AArch64::ANDSXrr: in expandMI()
1238 case AArch64::BICSWrr: in expandMI()
1239 case AArch64::BICSXrr: in expandMI()
1240 case AArch64::EONWrr: in expandMI()
1241 case AArch64::EONXrr: in expandMI()
1242 case AArch64::EORWrr: in expandMI()
1243 case AArch64::EORXrr: in expandMI()
1244 case AArch64::ORNWrr: in expandMI()
1245 case AArch64::ORNXrr: in expandMI()
1246 case AArch64::ORRWrr: in expandMI()
1247 case AArch64::ORRXrr: { in expandMI()
1252 case AArch64::ADDWrr: Opcode = AArch64::ADDWrs; break; in expandMI()
1253 case AArch64::SUBWrr: Opcode = AArch64::SUBWrs; break; in expandMI()
1254 case AArch64::ADDXrr: Opcode = AArch64::ADDXrs; break; in expandMI()
1255 case AArch64::SUBXrr: Opcode = AArch64::SUBXrs; break; in expandMI()
1256 case AArch64::ADDSWrr: Opcode = AArch64::ADDSWrs; break; in expandMI()
1257 case AArch64::SUBSWrr: Opcode = AArch64::SUBSWrs; break; in expandMI()
1258 case AArch64::ADDSXrr: Opcode = AArch64::ADDSXrs; break; in expandMI()
1259 case AArch64::SUBSXrr: Opcode = AArch64::SUBSXrs; break; in expandMI()
1260 case AArch64::ANDWrr: Opcode = AArch64::ANDWrs; break; in expandMI()
1261 case AArch64::ANDXrr: Opcode = AArch64::ANDXrs; break; in expandMI()
1262 case AArch64::BICWrr: Opcode = AArch64::BICWrs; break; in expandMI()
1263 case AArch64::BICXrr: Opcode = AArch64::BICXrs; break; in expandMI()
1264 case AArch64::ANDSWrr: Opcode = AArch64::ANDSWrs; break; in expandMI()
1265 case AArch64::ANDSXrr: Opcode = AArch64::ANDSXrs; break; in expandMI()
1266 case AArch64::BICSWrr: Opcode = AArch64::BICSWrs; break; in expandMI()
1267 case AArch64::BICSXrr: Opcode = AArch64::BICSXrs; break; in expandMI()
1268 case AArch64::EONWrr: Opcode = AArch64::EONWrs; break; in expandMI()
1269 case AArch64::EONXrr: Opcode = AArch64::EONXrs; break; in expandMI()
1270 case AArch64::EORWrr: Opcode = AArch64::EORWrs; break; in expandMI()
1271 case AArch64::EORXrr: Opcode = AArch64::EORXrs; break; in expandMI()
1272 case AArch64::ORNWrr: Opcode = AArch64::ORNWrs; break; in expandMI()
1273 case AArch64::ORNXrr: Opcode = AArch64::ORNXrs; break; in expandMI()
1274 case AArch64::ORRWrr: Opcode = AArch64::ORRWrs; break; in expandMI()
1275 case AArch64::ORRXrr: Opcode = AArch64::ORRXrs; break; in expandMI()
1295 case AArch64::LOADgot: { in expandMI()
1304 TII->get(AArch64::LDRXl), DstReg); in expandMI()
1320 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg); in expandMI()
1325 unsigned Reg32 = TRI->getSubReg(DstReg, AArch64::sub_32); in expandMI()
1327 MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::LDRWui)) in expandMI()
1333 MIB2 = BuildMI(MBB, MBBI, DL, TII->get(AArch64::LDRXui)) in expandMI()
1362 case AArch64::MOVaddrBA: { in expandMI()
1376 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg) in expandMI()
1379 TII->get(AArch64::LDRXui), DstReg) in expandMI()
1389 case AArch64::MOVaddr: in expandMI()
1390 case AArch64::MOVaddrJT: in expandMI()
1391 case AArch64::MOVaddrCP: in expandMI()
1392 case AArch64::MOVaddrTLS: in expandMI()
1393 case AArch64::MOVaddrEXT: { in expandMI()
1396 assert(DstReg != AArch64::XZR); in expandMI()
1398 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg) in expandMI()
1412 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi), DstReg) in expandMI()
1419 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri)) in expandMI()
1429 case AArch64::ADDlowTLS: in expandMI()
1431 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri)) in expandMI()
1439 case AArch64::MOVbaseTLS: { in expandMI()
1451 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg) in expandMI()
1457 case AArch64::MOVi32imm: in expandMI()
1459 case AArch64::MOVi64imm: in expandMI()
1461 case AArch64::RET_ReallyLR: { in expandMI()
1468 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET)) in expandMI()
1469 .addReg(AArch64::LR, RegState::Undef); in expandMI()
1474 case AArch64::CMP_SWAP_8: in expandMI()
1475 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRB, AArch64::STLXRB, in expandMI()
1476 AArch64::SUBSWrx, in expandMI()
1478 AArch64::WZR, NextMBBI); in expandMI()
1479 case AArch64::CMP_SWAP_16: in expandMI()
1480 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRH, AArch64::STLXRH, in expandMI()
1481 AArch64::SUBSWrx, in expandMI()
1483 AArch64::WZR, NextMBBI); in expandMI()
1484 case AArch64::CMP_SWAP_32: in expandMI()
1485 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRW, AArch64::STLXRW, in expandMI()
1486 AArch64::SUBSWrs, in expandMI()
1488 AArch64::WZR, NextMBBI); in expandMI()
1489 case AArch64::CMP_SWAP_64: in expandMI()
1491 AArch64::LDAXRX, AArch64::STLXRX, AArch64::SUBSXrs, in expandMI()
1493 AArch64::XZR, NextMBBI); in expandMI()
1494 case AArch64::CMP_SWAP_128: in expandMI()
1495 case AArch64::CMP_SWAP_128_RELEASE: in expandMI()
1496 case AArch64::CMP_SWAP_128_ACQUIRE: in expandMI()
1497 case AArch64::CMP_SWAP_128_MONOTONIC: in expandMI()
1500 case AArch64::AESMCrrTied: in expandMI()
1501 case AArch64::AESIMCrrTied: { in expandMI()
1504 TII->get(Opcode == AArch64::AESMCrrTied ? AArch64::AESMCrr : in expandMI()
1505 AArch64::AESIMCrr)) in expandMI()
1512 case AArch64::IRGstack: { in expandMI()
1534 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::IRG)) in expandMI()
1541 case AArch64::TAGPstack: { in expandMI()
1544 TII->get(Offset >= 0 ? AArch64::ADDG : AArch64::SUBG)) in expandMI()
1552 case AArch64::STGloop_wback: in expandMI()
1553 case AArch64::STZGloop_wback: in expandMI()
1555 case AArch64::STGloop: in expandMI()
1556 case AArch64::STZGloop: in expandMI()
1560 case AArch64::STR_ZZZZXI: in expandMI()
1561 return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 4); in expandMI()
1562 case AArch64::STR_ZZZXI: in expandMI()
1563 return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 3); in expandMI()
1564 case AArch64::STR_ZZXI: in expandMI()
1565 return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 2); in expandMI()
1566 case AArch64::STR_PPXI: in expandMI()
1567 return expandSVESpillFill(MBB, MBBI, AArch64::STR_PXI, 2); in expandMI()
1568 case AArch64::LDR_ZZZZXI: in expandMI()
1569 return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 4); in expandMI()
1570 case AArch64::LDR_ZZZXI: in expandMI()
1571 return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 3); in expandMI()
1572 case AArch64::LDR_ZZXI: in expandMI()
1573 return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 2); in expandMI()
1574 case AArch64::LDR_PPXI: in expandMI()
1575 return expandSVESpillFill(MBB, MBBI, AArch64::LDR_PXI, 2); in expandMI()
1576 case AArch64::BLR_RVMARKER: in expandMI()
1577 case AArch64::BLRA_RVMARKER: in expandMI()
1579 case AArch64::BLR_BTI: in expandMI()
1581 case AArch64::StoreSwiftAsyncContext: in expandMI()
1583 case AArch64::RestoreZAPseudo: { in expandMI()
1589 case AArch64::MSRpstatePseudo: { in expandMI()
1595 case AArch64::COALESCER_BARRIER_FPR16: in expandMI()
1596 case AArch64::COALESCER_BARRIER_FPR32: in expandMI()
1597 case AArch64::COALESCER_BARRIER_FPR64: in expandMI()
1598 case AArch64::COALESCER_BARRIER_FPR128: in expandMI()
1601 case AArch64::LD1B_2Z_IMM_PSEUDO: in expandMI()
1603 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1604 AArch64::LD1B_2Z_IMM, AArch64::LD1B_2Z_STRIDED_IMM); in expandMI()
1605 case AArch64::LD1H_2Z_IMM_PSEUDO: in expandMI()
1607 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1608 AArch64::LD1H_2Z_IMM, AArch64::LD1H_2Z_STRIDED_IMM); in expandMI()
1609 case AArch64::LD1W_2Z_IMM_PSEUDO: in expandMI()
1611 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1612 AArch64::LD1W_2Z_IMM, AArch64::LD1W_2Z_STRIDED_IMM); in expandMI()
1613 case AArch64::LD1D_2Z_IMM_PSEUDO: in expandMI()
1615 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1616 AArch64::LD1D_2Z_IMM, AArch64::LD1D_2Z_STRIDED_IMM); in expandMI()
1617 case AArch64::LDNT1B_2Z_IMM_PSEUDO: in expandMI()
1619 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1620 AArch64::LDNT1B_2Z_IMM, AArch64::LDNT1B_2Z_STRIDED_IMM); in expandMI()
1621 case AArch64::LDNT1H_2Z_IMM_PSEUDO: in expandMI()
1623 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1624 AArch64::LDNT1H_2Z_IMM, AArch64::LDNT1H_2Z_STRIDED_IMM); in expandMI()
1625 case AArch64::LDNT1W_2Z_IMM_PSEUDO: in expandMI()
1627 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1628 AArch64::LDNT1W_2Z_IMM, AArch64::LDNT1W_2Z_STRIDED_IMM); in expandMI()
1629 case AArch64::LDNT1D_2Z_IMM_PSEUDO: in expandMI()
1631 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1632 AArch64::LDNT1D_2Z_IMM, AArch64::LDNT1D_2Z_STRIDED_IMM); in expandMI()
1633 case AArch64::LD1B_2Z_PSEUDO: in expandMI()
1634 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass, in expandMI()
1635 AArch64::ZPR2StridedRegClass, AArch64::LD1B_2Z, in expandMI()
1636 AArch64::LD1B_2Z_STRIDED); in expandMI()
1637 case AArch64::LD1H_2Z_PSEUDO: in expandMI()
1638 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass, in expandMI()
1639 AArch64::ZPR2StridedRegClass, AArch64::LD1H_2Z, in expandMI()
1640 AArch64::LD1H_2Z_STRIDED); in expandMI()
1641 case AArch64::LD1W_2Z_PSEUDO: in expandMI()
1642 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass, in expandMI()
1643 AArch64::ZPR2StridedRegClass, AArch64::LD1W_2Z, in expandMI()
1644 AArch64::LD1W_2Z_STRIDED); in expandMI()
1645 case AArch64::LD1D_2Z_PSEUDO: in expandMI()
1646 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass, in expandMI()
1647 AArch64::ZPR2StridedRegClass, AArch64::LD1D_2Z, in expandMI()
1648 AArch64::LD1D_2Z_STRIDED); in expandMI()
1649 case AArch64::LDNT1B_2Z_PSEUDO: in expandMI()
1651 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1652 AArch64::LDNT1B_2Z, AArch64::LDNT1B_2Z_STRIDED); in expandMI()
1653 case AArch64::LDNT1H_2Z_PSEUDO: in expandMI()
1655 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1656 AArch64::LDNT1H_2Z, AArch64::LDNT1H_2Z_STRIDED); in expandMI()
1657 case AArch64::LDNT1W_2Z_PSEUDO: in expandMI()
1659 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1660 AArch64::LDNT1W_2Z, AArch64::LDNT1W_2Z_STRIDED); in expandMI()
1661 case AArch64::LDNT1D_2Z_PSEUDO: in expandMI()
1663 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass, in expandMI()
1664 AArch64::LDNT1D_2Z, AArch64::LDNT1D_2Z_STRIDED); in expandMI()
1665 case AArch64::LD1B_4Z_IMM_PSEUDO: in expandMI()
1667 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1668 AArch64::LD1B_4Z_IMM, AArch64::LD1B_4Z_STRIDED_IMM); in expandMI()
1669 case AArch64::LD1H_4Z_IMM_PSEUDO: in expandMI()
1671 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1672 AArch64::LD1H_4Z_IMM, AArch64::LD1H_4Z_STRIDED_IMM); in expandMI()
1673 case AArch64::LD1W_4Z_IMM_PSEUDO: in expandMI()
1675 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1676 AArch64::LD1W_4Z_IMM, AArch64::LD1W_4Z_STRIDED_IMM); in expandMI()
1677 case AArch64::LD1D_4Z_IMM_PSEUDO: in expandMI()
1679 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1680 AArch64::LD1D_4Z_IMM, AArch64::LD1D_4Z_STRIDED_IMM); in expandMI()
1681 case AArch64::LDNT1B_4Z_IMM_PSEUDO: in expandMI()
1683 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1684 AArch64::LDNT1B_4Z_IMM, AArch64::LDNT1B_4Z_STRIDED_IMM); in expandMI()
1685 case AArch64::LDNT1H_4Z_IMM_PSEUDO: in expandMI()
1687 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1688 AArch64::LDNT1H_4Z_IMM, AArch64::LDNT1H_4Z_STRIDED_IMM); in expandMI()
1689 case AArch64::LDNT1W_4Z_IMM_PSEUDO: in expandMI()
1691 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1692 AArch64::LDNT1W_4Z_IMM, AArch64::LDNT1W_4Z_STRIDED_IMM); in expandMI()
1693 case AArch64::LDNT1D_4Z_IMM_PSEUDO: in expandMI()
1695 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1696 AArch64::LDNT1D_4Z_IMM, AArch64::LDNT1D_4Z_STRIDED_IMM); in expandMI()
1697 case AArch64::LD1B_4Z_PSEUDO: in expandMI()
1698 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass, in expandMI()
1699 AArch64::ZPR4StridedRegClass, AArch64::LD1B_4Z, in expandMI()
1700 AArch64::LD1B_4Z_STRIDED); in expandMI()
1701 case AArch64::LD1H_4Z_PSEUDO: in expandMI()
1702 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass, in expandMI()
1703 AArch64::ZPR4StridedRegClass, AArch64::LD1H_4Z, in expandMI()
1704 AArch64::LD1H_4Z_STRIDED); in expandMI()
1705 case AArch64::LD1W_4Z_PSEUDO: in expandMI()
1706 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass, in expandMI()
1707 AArch64::ZPR4StridedRegClass, AArch64::LD1W_4Z, in expandMI()
1708 AArch64::LD1W_4Z_STRIDED); in expandMI()
1709 case AArch64::LD1D_4Z_PSEUDO: in expandMI()
1710 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass, in expandMI()
1711 AArch64::ZPR4StridedRegClass, AArch64::LD1D_4Z, in expandMI()
1712 AArch64::LD1D_4Z_STRIDED); in expandMI()
1713 case AArch64::LDNT1B_4Z_PSEUDO: in expandMI()
1715 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1716 AArch64::LDNT1B_4Z, AArch64::LDNT1B_4Z_STRIDED); in expandMI()
1717 case AArch64::LDNT1H_4Z_PSEUDO: in expandMI()
1719 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1720 AArch64::LDNT1H_4Z, AArch64::LDNT1H_4Z_STRIDED); in expandMI()
1721 case AArch64::LDNT1W_4Z_PSEUDO: in expandMI()
1723 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1724 AArch64::LDNT1W_4Z, AArch64::LDNT1W_4Z_STRIDED); in expandMI()
1725 case AArch64::LDNT1D_4Z_PSEUDO: in expandMI()
1727 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass, in expandMI()
1728 AArch64::LDNT1D_4Z, AArch64::LDNT1D_4Z_STRIDED); in expandMI()