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/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
43 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
[all …]
/linux/include/soc/mscc/
H A Docelot_dev.h11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
23 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
[all …]
H A Docelot_hsio.h85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
109 #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h11 #define MTK_DP_HPD_DISCONNECT BIT(1)
12 #define MTK_DP_HPD_CONNECT BIT(2)
13 #define MTK_DP_HPD_INTERRUPT BIT(3)
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
22 #define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)
23 #define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)
24 #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
25 #define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)
26 #define DA_CKM_CKTX0_EN_FORCE_EN BIT(10)
27 #define DA_CKM_XTAL_CK_FORCE_VAL BIT(9)
[all …]
/linux/drivers/clk/stm32/
H A Dstm32mp13_rcc.h219 #define RCC_SECCFGR_PLL12SEC 8
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
245 #define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8)
246 #define RCC_MP_APRSTCR_RSTTO_SHIFT 8
249 #define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8)
250 #define RCC_MP_APRSTSR_RSTTOV_SHIFT 8
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
[all …]
/linux/drivers/clk/renesas/
H A Dr9a09g047-cpg.c76 {3, 8},
89 {2, 8},
97 {2, 8},
145 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
155 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
198 BUS_MSTOP(5, BIT(9))),
200 BUS_MSTOP(3, BIT(2))),
202 BUS_MSTOP(3, BIT(3))),
204 BUS_MSTOP(10, BIT(11))),
206 BUS_MSTOP(10, BIT(12))),
[all …]
H A Dr9a09g056-cpg.c78 {3, 8},
91 {2, 8},
100 {3, 8},
105 {8, 18},
119 {2, 8},
179 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
185 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
235 BUS_MSTOP(3, BIT(5))),
237 BUS_MSTOP(5, BIT(10))),
239 BUS_MSTOP(5, BIT(11))),
[all …]
H A Dr9a09g057-cpg.c82 {3, 8},
95 {2, 8},
104 {3, 8},
109 {8, 18},
123 {2, 8},
183 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
189 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
246 BUS_MSTOP(5, BIT(9))),
248 BUS_MSTOP(3, BIT(2))),
250 BUS_MSTOP(3, BIT(3))),
[all …]
/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h40 #define B0_RAP 0x0000 /* 8 bit register address port */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
47 #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h18 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
19 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
27 #define MT_EFUSE_CTRL_KICK BIT(30)
28 #define MT_EFUSE_CTRL_SEL BIT(31)
34 #define MT_COEXCFG0_COEX_EN BIT(0)
37 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
38 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
39 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
41 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/linux/drivers/pmdomain/mediatek/
H A Dmt6893-pm-domains.h27 #define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(7)
29 #define MT6893_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(24)
30 #define MT6893_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(25)
31 #define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(6)
32 #define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(7)
33 #define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP1 BIT(26)
34 #define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2 BIT(0)
35 #define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP3 BIT(27)
36 #define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP4 BIT(1)
39 #define MT6893_TOP_AXI_PROT_EN_MDP_STEP1 BIT(10)
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
38 #define PDN_DAC_MASK_SFT BIT(25)
40 #define PDN_ADC_MASK_SFT BIT(24)
42 #define PDN_TDM_CK_MASK_SFT BIT(20)
[all …]
/linux/drivers/net/ethernet/asix/
H A Dax88796c_main.h31 #define AX_MCAST_FILTER_SIZE 8
121 #define AX_FC_RX BIT(0)
122 #define AX_FC_TX BIT(1)
123 #define AX_FC_ANEG BIT(2)
126 #define AX_CAP_COMP BIT(0)
153 #define PSR_DEV_READY BIT(7)
155 #define PSR_RESET_CLR BIT(15)
158 #define FER_IPALM BIT(0)
159 #define FER_DCRC BIT(1)
160 #define FER_RH3M BIT(2)
[all …]
/linux/sound/soc/codecs/
H A Dmt6357.h14 /* Reg bit defines */
16 #define MT6357_GPIO8_DIR_MASK BIT(8)
18 #define MT6357_GPIO8_DIR_OUTPUT BIT(8)
19 #define MT6357_GPIO9_DIR_MASK BIT(9)
21 #define MT6357_GPIO9_DIR_OUTPUT BIT(9)
22 #define MT6357_GPIO10_DIR_MASK BIT(10)
24 #define MT6357_GPIO10_DIR_OUTPUT BIT(10)
25 #define MT6357_GPIO11_DIR_MASK BIT(11)
27 #define MT6357_GPIO11_DIR_OUTPUT BIT(11)
28 #define MT6357_GPIO12_DIR_MASK BIT(12)
[all …]
/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h40 ('3' << 8) | \
51 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
52 # define V3D_IDENT1_QUPS_SHIFT 8
61 # define V3D_L2CACTL_L2CCLR BIT(2)
62 # define V3D_L2CACTL_L2CDIS BIT(1)
63 # define V3D_L2CACTL_L2CENA BIT(0)
70 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
71 # define V3D_SLCACTL_UCC_SHIFT 8
78 # define V3D_INT_SPILLUSE BIT(3)
79 # define V3D_INT_OUTOMEM BIT(2)
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dskge.h131 /* B0_CTST 16 bit Control/Status register */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
168 /* Bit 30: reserved */
195 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
[all …]
H A Dsky2.h41 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
48 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
49 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
50 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
52 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
53 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
57 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
73 P_CLK_PCI_REGS_D3_DIS = 1<<8, /* Disable Clock PCI Regs D3 */
91 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
[all …]
/linux/drivers/staging/vme_user/
H A Dvme_tsi148.h26 #define TSI148_MAX_MASTER 8 /* Max Master Windows */
27 #define TSI148_MAX_SLAVE 8 /* Max Slave Windows */
30 #define TSI148_MAX_SEMAPHORE 8 /* Max Semaphores */
53 * correctly laid out - It must also be aligned on 64-bit boundaries.
70 * The descriptor needs to be aligned on a 64-bit boundary, we increase
79 * TSI148 ASIC register structure overlays and bit field definitions.
193 static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1,
219 static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
349 static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
529 * TSI148 Register Bit Definitions
[all …]
/linux/drivers/media/cec/platform/tegra/
H A Dtegra_cec.h37 #define TEGRA_CEC_HWCTRL_RX_SNOOP BIT(15)
38 #define TEGRA_CEC_HWCTRL_RX_NAK_MODE BIT(16)
39 #define TEGRA_CEC_HWCTRL_TX_NAK_MODE BIT(24)
40 #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE BIT(30)
41 #define TEGRA_CEC_HWCTRL_TX_RX_MODE BIT(31)
43 #define TEGRA_CEC_INPUT_FILTER_MODE BIT(31)
47 #define TEGRA_CEC_TX_REG_EOM BIT(8)
48 #define TEGRA_CEC_TX_REG_BCAST BIT(12)
49 #define TEGRA_CEC_TX_REG_START_BIT BIT(16)
50 #define TEGRA_CEC_TX_REG_RETRY BIT(17)
[all …]
/linux/drivers/power/supply/
H A Dbd99954-charger.h482 [F_PREV_CHGSTM_STATE] = REG_FIELD(CHGSTM_STATUS, 8, 14),
486 [F_BATTEMP] = REG_FIELD(CHGOP_STATUS, 8, 10),
490 [F_THERMWDT_VAL] = REG_FIELD(WDT_STATUS, 8, 15),
513 [F_SDP_CHG_TRIG] = REG_FIELD(CHGOP_SET1, 8, 8),
520 [F_BATT_LEARN] = REG_FIELD(CHGOP_SET2, 8, 8),
530 [F_WDT_FST] = REG_FIELD(CHGWDT_SET, 8, 15),
532 [F_WDT_IBAT_SHORT] = REG_FIELD(BATTWDT_SET, 8, 15),
551 [F_PROCHOT_IDCHG_DG_SET] = REG_FIELD(PROCHOT_CTRL_SET, 8, 9),
558 [F_PMON_INSEL] = REG_FIELD(PMON_IOUT_CTRL_SET, 8, 8),
567 [F_VCC_ADCRTRY] = REG_FIELD(VCC_UCD_SET, 8, 8),
[all …]
/linux/drivers/mmc/host/
H A Dtoshsd.h24 #define SD_PCICFG_EXTGATECLK3 0xf9 /* Bit 1: double buffer/single buffer */
28 #define SD_PCICFG_CLKMODE_DIV_DISABLE BIT(0)
74 #define SD_TRANSCTL_SET BIT(8)
76 #define SD_CARDCLK_DIV_DISABLE BIT(15)
77 #define SD_CARDCLK_ENABLE_CLOCK BIT(8)
78 #define SD_CARDCLK_CLK_DIV_512 BIT(7)
79 #define SD_CARDCLK_CLK_DIV_256 BIT(6)
80 #define SD_CARDCLK_CLK_DIV_128 BIT(5)
81 #define SD_CARDCLK_CLK_DIV_64 BIT(4)
82 #define SD_CARDCLK_CLK_DIV_32 BIT(3)
[all …]
/linux/Documentation/gpu/
H A Dafbc.rst42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
50 * Component 1: G(8)
51 * Component 2: B(8)
55 * Component 0: Y(8)
56 * Component 1: Cb(8, 2x1 subsampled)
57 * Component 2: Cr(8, 2x1 subsampled)
[all …]
/linux/include/sound/
H A Dump_msg.h8 /* MIDI 1.0 / 2.0 Status Code (4bit) */
27 /* MIDI 1.0 Channel Control (7bit) */
36 UMP_CC_BALANCE = 8,
128 /* MIDI 1.0 Note Off / Note On (32bit) */
135 u32 note:8;
136 u32 velocity:8;
138 u32 velocity:8;
139 u32 note:8;
147 /* MIDI 1.0 Poly Pressure (32bit) */
154 u32 note:8;
[all …]
/linux/drivers/net/dsa/b53/
H A Db53_regs.h67 /* Port Control Register (8 bit) */
69 #define PORT_CTRL_RX_DISABLE BIT(0)
70 #define PORT_CTRL_TX_DISABLE BIT(1)
71 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
72 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
73 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
83 /* SMP Control Register (8 bit) */
86 /* Switch Mode Control Register (8 bit) */
88 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
89 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
[all …]
/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_regs.h38 #define VE_MODE_PIC_WIDTH_IS_4096 BIT(22)
39 #define VE_MODE_PIC_WIDTH_MORE_2048 BIT(21)
96 #define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y) (24 - 4 * (y) - 8 * (x))
103 SHIFT_AND_MASK_BITS(s, 9, 8)
105 ((v) ? BIT(7) : 0)
107 ((v) ? BIT(6) : 0)
109 ((v) ? BIT(5) : 0)
111 ((v) ? BIT(4) : 0)
113 ((v) ? BIT(3) : 0)
115 ((v) ? BIT(2) : 0)
[all …]

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