xref: /linux/drivers/mmc/host/toshsd.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2a5eb8bbdSOndrej Zary /*
3a5eb8bbdSOndrej Zary  *  Toshiba PCI Secure Digital Host Controller Interface driver
4a5eb8bbdSOndrej Zary  *
5a5eb8bbdSOndrej Zary  *  Copyright (C) 2014 Ondrej Zary
6a5eb8bbdSOndrej Zary  *  Copyright (C) 2007 Richard Betts, All Rights Reserved.
7a5eb8bbdSOndrej Zary  *
8a5eb8bbdSOndrej Zary  *      Based on asic3_mmc.c Copyright (c) 2005 SDG Systems, LLC
9a5eb8bbdSOndrej Zary  */
10a5eb8bbdSOndrej Zary 
11a5eb8bbdSOndrej Zary #define HCLK	33000000	/* 33 MHz (PCI clock) */
12a5eb8bbdSOndrej Zary 
13a5eb8bbdSOndrej Zary #define SD_PCICFG_CLKSTOP	0x40	/* 0x1f = clock controller, 0 = stop */
14a5eb8bbdSOndrej Zary #define SD_PCICFG_GATEDCLK	0x41	/* Gated clock */
15a5eb8bbdSOndrej Zary #define SD_PCICFG_CLKMODE	0x42	/* Control clock of SD controller */
16a5eb8bbdSOndrej Zary #define SD_PCICFG_PINSTATUS	0x44	/* R/O: read status of SD pins */
17a5eb8bbdSOndrej Zary #define SD_PCICFG_POWER1	0x48
18a5eb8bbdSOndrej Zary #define SD_PCICFG_POWER2	0x49
19a5eb8bbdSOndrej Zary #define SD_PCICFG_POWER3	0x4a
20a5eb8bbdSOndrej Zary #define SD_PCICFG_CARDDETECT	0x4c
21a5eb8bbdSOndrej Zary #define SD_PCICFG_SLOTS		0x50	/* R/O: define support slot number */
22a5eb8bbdSOndrej Zary #define SD_PCICFG_EXTGATECLK1	0xf0	/* Could be used for gated clock */
23a5eb8bbdSOndrej Zary #define SD_PCICFG_EXTGATECLK2	0xf1	/* Could be used for gated clock */
24a5eb8bbdSOndrej Zary #define SD_PCICFG_EXTGATECLK3	0xf9	/* Bit 1: double buffer/single buffer */
25a5eb8bbdSOndrej Zary #define SD_PCICFG_SDLED_ENABLE1	0xfa
26a5eb8bbdSOndrej Zary #define SD_PCICFG_SDLED_ENABLE2	0xfe
27a5eb8bbdSOndrej Zary 
28a5eb8bbdSOndrej Zary #define SD_PCICFG_CLKMODE_DIV_DISABLE	BIT(0)
29a5eb8bbdSOndrej Zary #define SD_PCICFG_CLKSTOP_ENABLE_ALL	0x1f
30a5eb8bbdSOndrej Zary #define SD_PCICFG_LED_ENABLE1_START	0x12
31a5eb8bbdSOndrej Zary #define SD_PCICFG_LED_ENABLE2_START	0x80
32a5eb8bbdSOndrej Zary 
33a5eb8bbdSOndrej Zary #define SD_PCICFG_PWR1_33V	0x08	/* Set for 3.3 volts */
34a5eb8bbdSOndrej Zary #define SD_PCICFG_PWR1_OFF	0x00	/* Turn off power */
35a5eb8bbdSOndrej Zary #define SD_PCICFG_PWR2_AUTO	0x02
36a5eb8bbdSOndrej Zary 
37a5eb8bbdSOndrej Zary #define SD_CMD			0x00	/* also for SDIO */
38a5eb8bbdSOndrej Zary #define SD_ARG0			0x04	/* also for SDIO */
39a5eb8bbdSOndrej Zary #define SD_ARG1			0x06	/* also for SDIO */
40a5eb8bbdSOndrej Zary #define SD_STOPINTERNAL		0x08
41a5eb8bbdSOndrej Zary #define SD_BLOCKCOUNT		0x0a	/* also for SDIO */
42a5eb8bbdSOndrej Zary #define SD_RESPONSE0		0x0c	/* also for SDIO */
43a5eb8bbdSOndrej Zary #define SD_RESPONSE1		0x0e	/* also for SDIO */
44a5eb8bbdSOndrej Zary #define SD_RESPONSE2		0x10	/* also for SDIO */
45a5eb8bbdSOndrej Zary #define SD_RESPONSE3		0x12	/* also for SDIO */
46a5eb8bbdSOndrej Zary #define SD_RESPONSE4		0x14	/* also for SDIO */
47a5eb8bbdSOndrej Zary #define SD_RESPONSE5		0x16	/* also for SDIO */
48a5eb8bbdSOndrej Zary #define SD_RESPONSE6		0x18	/* also for SDIO */
49a5eb8bbdSOndrej Zary #define SD_RESPONSE7		0x1a	/* also for SDIO */
50a5eb8bbdSOndrej Zary #define SD_CARDSTATUS		0x1c	/* also for SDIO */
51a5eb8bbdSOndrej Zary #define SD_BUFFERCTRL		0x1e	/* also for SDIO */
52a5eb8bbdSOndrej Zary #define SD_INTMASKCARD		0x20	/* also for SDIO */
53a5eb8bbdSOndrej Zary #define SD_INTMASKBUFFER	0x22	/* also for SDIO */
54a5eb8bbdSOndrej Zary #define SD_CARDCLOCKCTRL	0x24
55a5eb8bbdSOndrej Zary #define SD_CARDXFERDATALEN	0x26	/* also for SDIO */
56a5eb8bbdSOndrej Zary #define SD_CARDOPTIONSETUP	0x28	/* also for SDIO */
57a5eb8bbdSOndrej Zary #define SD_ERRORSTATUS0		0x2c	/* also for SDIO */
58a5eb8bbdSOndrej Zary #define SD_ERRORSTATUS1		0x2e	/* also for SDIO */
59a5eb8bbdSOndrej Zary #define SD_DATAPORT		0x30	/* also for SDIO */
60a5eb8bbdSOndrej Zary #define SD_TRANSACTIONCTRL	0x34	/* also for SDIO */
61a5eb8bbdSOndrej Zary #define SD_SOFTWARERESET	0xe0	/* also for SDIO */
62a5eb8bbdSOndrej Zary 
63a5eb8bbdSOndrej Zary /* registers above marked "also for SDIO" and all SDIO registers below can be
64a5eb8bbdSOndrej Zary  * accessed at SDIO_BASE + reg address */
65a5eb8bbdSOndrej Zary #define SDIO_BASE	 0x100
66a5eb8bbdSOndrej Zary 
67a5eb8bbdSOndrej Zary #define SDIO_CARDPORTSEL	0x02
68a5eb8bbdSOndrej Zary #define SDIO_CARDINTCTRL	0x36
69a5eb8bbdSOndrej Zary #define SDIO_CLOCKNWAITCTRL	0x38
70a5eb8bbdSOndrej Zary #define SDIO_HOSTINFORMATION	0x3a
71a5eb8bbdSOndrej Zary #define SDIO_ERRORCTRL		0x3c
72a5eb8bbdSOndrej Zary #define SDIO_LEDCTRL		0x3e
73a5eb8bbdSOndrej Zary 
74a5eb8bbdSOndrej Zary #define SD_TRANSCTL_SET		BIT(8)
75a5eb8bbdSOndrej Zary 
76a5eb8bbdSOndrej Zary #define SD_CARDCLK_DIV_DISABLE	BIT(15)
77a5eb8bbdSOndrej Zary #define SD_CARDCLK_ENABLE_CLOCK	BIT(8)
78a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_512	BIT(7)
79a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_256	BIT(6)
80a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_128	BIT(5)
81a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_64	BIT(4)
82a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_32	BIT(3)
83a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_16	BIT(2)
84a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_8	BIT(1)
85a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_4	BIT(0)
86a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_2	0
87a5eb8bbdSOndrej Zary 
88a5eb8bbdSOndrej Zary #define SD_CARDOPT_REQUIRED		0x000e
89a5eb8bbdSOndrej Zary #define SD_CARDOPT_DATA_RESP_TIMEOUT(x)	(((x) & 0x0f) << 4) /* 4 bits */
90a5eb8bbdSOndrej Zary #define SD_CARDOPT_C2_MODULE_ABSENT	BIT(14)
91a5eb8bbdSOndrej Zary #define SD_CARDOPT_DATA_XFR_WIDTH_1	(1 << 15)
92a5eb8bbdSOndrej Zary #define SD_CARDOPT_DATA_XFR_WIDTH_4	(0 << 15)
93a5eb8bbdSOndrej Zary 
94a5eb8bbdSOndrej Zary #define SD_CMD_TYPE_CMD			(0 << 6)
95a5eb8bbdSOndrej Zary #define SD_CMD_TYPE_ACMD		(1 << 6)
96a5eb8bbdSOndrej Zary #define SD_CMD_TYPE_AUTHEN		(2 << 6)
97a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_NONE		(3 << 8)
98a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R1		(4 << 8)
99a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R1B	(5 << 8)
100a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R2		(6 << 8)
101a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R3		(7 << 8)
102a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R6		(4 << 8)
103a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R7		(4 << 8)
104a5eb8bbdSOndrej Zary #define SD_CMD_DATA_PRESENT		BIT(11)
105a5eb8bbdSOndrej Zary #define SD_CMD_TRANSFER_READ		BIT(12)
106a5eb8bbdSOndrej Zary #define SD_CMD_MULTI_BLOCK		BIT(13)
107a5eb8bbdSOndrej Zary #define SD_CMD_SECURITY_CMD		BIT(14)
108a5eb8bbdSOndrej Zary 
109a5eb8bbdSOndrej Zary #define SD_STOPINT_ISSUE_CMD12		BIT(0)
110a5eb8bbdSOndrej Zary #define SD_STOPINT_AUTO_ISSUE_CMD12	BIT(8)
111a5eb8bbdSOndrej Zary 
112a5eb8bbdSOndrej Zary #define SD_CARD_RESP_END	BIT(0)
113a5eb8bbdSOndrej Zary #define SD_CARD_RW_END		BIT(2)
114a5eb8bbdSOndrej Zary #define SD_CARD_CARD_REMOVED_0	BIT(3)
115a5eb8bbdSOndrej Zary #define SD_CARD_CARD_INSERTED_0	BIT(4)
116a5eb8bbdSOndrej Zary #define SD_CARD_PRESENT_0	BIT(5)
117a5eb8bbdSOndrej Zary #define SD_CARD_UNK6		BIT(6)
118a5eb8bbdSOndrej Zary #define SD_CARD_WRITE_PROTECT	BIT(7)
119a5eb8bbdSOndrej Zary #define SD_CARD_CARD_REMOVED_3	BIT(8)
120a5eb8bbdSOndrej Zary #define SD_CARD_CARD_INSERTED_3	BIT(9)
121a5eb8bbdSOndrej Zary #define SD_CARD_PRESENT_3	BIT(10)
122a5eb8bbdSOndrej Zary 
123a5eb8bbdSOndrej Zary #define SD_BUF_CMD_INDEX_ERR	BIT(16)
124a5eb8bbdSOndrej Zary #define SD_BUF_CRC_ERR		BIT(17)
125a5eb8bbdSOndrej Zary #define SD_BUF_STOP_BIT_END_ERR	BIT(18)
126a5eb8bbdSOndrej Zary #define SD_BUF_DATA_TIMEOUT	BIT(19)
127a5eb8bbdSOndrej Zary #define SD_BUF_OVERFLOW		BIT(20)
128a5eb8bbdSOndrej Zary #define SD_BUF_UNDERFLOW	BIT(21)
129a5eb8bbdSOndrej Zary #define SD_BUF_CMD_TIMEOUT	BIT(22)
130a5eb8bbdSOndrej Zary #define SD_BUF_UNK7		BIT(23)
131a5eb8bbdSOndrej Zary #define SD_BUF_READ_ENABLE	BIT(24)
132a5eb8bbdSOndrej Zary #define SD_BUF_WRITE_ENABLE	BIT(25)
133a5eb8bbdSOndrej Zary #define SD_BUF_ILLEGAL_FUNCTION	BIT(29)
134a5eb8bbdSOndrej Zary #define SD_BUF_CMD_BUSY		BIT(30)
135a5eb8bbdSOndrej Zary #define SD_BUF_ILLEGAL_ACCESS	BIT(31)
136a5eb8bbdSOndrej Zary 
137a5eb8bbdSOndrej Zary #define SD_ERR0_RESP_CMD_ERR			BIT(0)
138a5eb8bbdSOndrej Zary #define SD_ERR0_RESP_NON_CMD12_END_BIT_ERR	BIT(2)
139a5eb8bbdSOndrej Zary #define SD_ERR0_RESP_CMD12_END_BIT_ERR		BIT(3)
140a5eb8bbdSOndrej Zary #define SD_ERR0_READ_DATA_END_BIT_ERR		BIT(4)
141a5eb8bbdSOndrej Zary #define SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR	BIT(5)
142a5eb8bbdSOndrej Zary #define SD_ERR0_RESP_NON_CMD12_CRC_ERR		BIT(8)
143a5eb8bbdSOndrej Zary #define SD_ERR0_RESP_CMD12_CRC_ERR		BIT(9)
144a5eb8bbdSOndrej Zary #define SD_ERR0_READ_DATA_CRC_ERR		BIT(10)
145a5eb8bbdSOndrej Zary #define SD_ERR0_WRITE_CMD_CRC_ERR		BIT(11)
146a5eb8bbdSOndrej Zary 
147a5eb8bbdSOndrej Zary #define SD_ERR1_NO_CMD_RESP		BIT(16)
148a5eb8bbdSOndrej Zary #define SD_ERR1_TIMEOUT_READ_DATA	BIT(20)
149a5eb8bbdSOndrej Zary #define SD_ERR1_TIMEOUT_CRS_STATUS	BIT(21)
150a5eb8bbdSOndrej Zary #define SD_ERR1_TIMEOUT_CRC_BUSY	BIT(22)
151a5eb8bbdSOndrej Zary 
152a5eb8bbdSOndrej Zary #define IRQ_DONT_CARE_BITS (SD_CARD_PRESENT_3 \
153a5eb8bbdSOndrej Zary 	| SD_CARD_WRITE_PROTECT \
154a5eb8bbdSOndrej Zary 	| SD_CARD_UNK6 \
155a5eb8bbdSOndrej Zary 	| SD_CARD_PRESENT_0 \
156a5eb8bbdSOndrej Zary 	| SD_BUF_UNK7 \
157a5eb8bbdSOndrej Zary 	| SD_BUF_CMD_BUSY)
158a5eb8bbdSOndrej Zary 
159a5eb8bbdSOndrej Zary struct toshsd_host {
160a5eb8bbdSOndrej Zary 	struct pci_dev *pdev;
161a5eb8bbdSOndrej Zary 	struct mmc_host *mmc;
162a5eb8bbdSOndrej Zary 
163a5eb8bbdSOndrej Zary 	spinlock_t lock;
164a5eb8bbdSOndrej Zary 
165a5eb8bbdSOndrej Zary 	struct mmc_request *mrq;/* Current request */
166a5eb8bbdSOndrej Zary 	struct mmc_command *cmd;/* Current command */
167a5eb8bbdSOndrej Zary 	struct mmc_data *data;	/* Current data request */
168a5eb8bbdSOndrej Zary 
169a5eb8bbdSOndrej Zary 	struct sg_mapping_iter sg_miter; /* for PIO */
170a5eb8bbdSOndrej Zary 
171a5eb8bbdSOndrej Zary 	void __iomem *ioaddr; /* mapped address */
172a5eb8bbdSOndrej Zary };
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