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/linux/arch/parisc/include/asm/
H A Dassembly.h16 #define REG_SZ 8
62 #define LDREGM ldd,mb
128 addib,NUV,n -1,1,.+8
278 fstd,ma %fr0, 8(\regs)
279 fstd,ma %fr1, 8(\regs)
280 fstd,ma %fr2, 8(\regs)
281 fstd,ma %fr3, 8(\regs)
282 fstd,ma %fr4, 8(\regs)
283 fstd,ma %fr5, 8(\regs)
284 fstd,ma %fr6, 8(\regs)
[all …]
H A Dbarrier.h16 #define mb() do { synchronize_caches(); } while (0) macro
17 #define rmb() mb()
18 #define wmb() mb()
19 #define dma_rmb() mb()
20 #define dma_wmb() mb()
22 #define mb() barrier() macro
29 #define __smp_mb() mb()
30 #define __smp_rmb() mb()
31 #define __smp_wmb() mb()
55 case 8: \
[all …]
/linux/drivers/mailbox/
H A Drockchip-mailbox.c17 #define MAILBOX_A2B_CMD(x) (0x08 + (x) * 8)
18 #define MAILBOX_A2B_DAT(x) (0x0c + (x) * 8)
22 #define MAILBOX_B2A_CMD(x) (0x30 + (x) * 8)
23 #define MAILBOX_B2A_DAT(x) (0x34 + (x) * 8)
38 struct rockchip_mbox *mb; member
53 struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev); in rockchip_mbox_send_data() local
55 struct rockchip_mbox_chan *chans = mb->chans; in rockchip_mbox_send_data()
60 if (msg->rx_size > mb->buf_size) { in rockchip_mbox_send_data()
61 dev_err(mb->mbox.dev, "Transmit size over buf size(%d)\n", in rockchip_mbox_send_data()
62 mb->buf_size); in rockchip_mbox_send_data()
[all …]
H A Daxiado-mailbox.c21 #define AXIADO_MBOX_TX_CHANS 8 /* 0-7 */
22 #define AXIADO_MBOX_RX_CHANS 8 /* 8-15 */
90 struct axiado_mbox *mb = dev_get_drvdata(chan->mbox->dev); in axiado_mbox_send_data() local
108 if (msg_len < sizeof(u32) || msg_len > mb->drv_data->msg_size) in axiado_mbox_send_data()
115 dev_warn_ratelimited(mb->mbox.dev, "Channel %u is busy\n", idx); in axiado_mbox_send_data()
129 dev_dbg(mb->mbox.dev, "%s: Ch-%u sent\n", __func__, idx); in axiado_mbox_send_data()
138 struct axiado_mbox *mb = dev_get_drvdata(chan->mbox->dev); in axiado_rx_thread() local
168 if (msg_len < sizeof(u32) || msg_len > mb->drv_data->msg_size) in axiado_rx_thread()
272 struct axiado_mbox *mb; in axiado_mbox_probe() local
282 mb = devm_kzalloc(dev, sizeof(*mb), GFP_KERNEL); in axiado_mbox_probe()
[all …]
H A Dcv1800-mailbox.c21 #define MAILBOX_MAX_CHAN 8
22 #define MAILBOX_MSG_LEN 8
165 struct cv1800_mbox *mb; in cv1800_mbox_probe() local
168 mb = devm_kzalloc(dev, sizeof(*mb), GFP_KERNEL); in cv1800_mbox_probe()
169 if (!mb) in cv1800_mbox_probe()
172 mb->mbox_base = devm_platform_ioremap_resource(pdev, 0); in cv1800_mbox_probe()
173 if (IS_ERR(mb->mbox_base)) in cv1800_mbox_probe()
174 return dev_err_probe(dev, PTR_ERR(mb->mbox_base), in cv1800_mbox_probe()
177 mb->mbox.dev = dev; in cv1800_mbox_probe()
178 mb->mbox.chans = mb->chans; in cv1800_mbox_probe()
[all …]
H A Dtegra-hsp.c25 #define HSP_INT_FULL_SHIFT 8
240 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; in tegra_hsp_shared_irq() local
242 if (mb->producer) { in tegra_hsp_shared_irq()
252 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); in tegra_hsp_shared_irq()
258 mbox_chan_txdone(mb->channel.chan, 0); in tegra_hsp_shared_irq()
266 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; in tegra_hsp_shared_irq() local
268 if (!mb->producer) in tegra_hsp_shared_irq()
269 mb->ops->recv(&mb->channel); in tegra_hsp_shared_irq()
463 struct tegra_hsp_mailbox *mb = chan->con_priv; in tegra_hsp_mailbox_send_data() local
464 struct tegra_hsp *hsp = mb->channel.hsp; in tegra_hsp_mailbox_send_data()
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/linux/arch/alpha/kernel/
H A Dcore_mcpcia.c27 * NOTE: Herein lie back-to-back mb instructions. They are magic.
54 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
60 * 10:8 Function number
66 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
72 * 23:16 bus number (8 bits = 128 possible buses)
74 * 10:8 function number
104 mb(); in conf_read()
108 mb(); in conf_read()
113 mb(); in conf_read()
117 mb(); in conf_read()
[all …]
H A Dcore_t2.c40 * floppy to DMA only via the scatter/gather window set up for 8MB
62 * NOTE: Herein lie back-to-back mb instructions. They are magic.
108 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
114 * 10:8 Function number
120 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
126 * 23:16 bus number (8 bits = 128 possible buses)
128 * 10:8 function number
156 if (device > 8) { in mk_conf_addr()
163 addr = (0x0800L << device) | ((device_fn & 7) << 8) | (where); in mk_conf_addr()
167 addr = (bus << 16) | (device_fn << 8) | (where); in mk_conf_addr()
[all …]
H A Dcore_polaris.c47 * 9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
52 * 23:16 bus number (8 bits = 128 possible buses)
54 * 10:8 function number
73 *pci_addr = (bus << 16) | (device_fn << 8) | (where) | in mk_conf_addr()
122 mb(); in polaris_write_config()
127 mb(); in polaris_write_config()
132 mb(); in polaris_write_config()
186 mb(); in polaris_pci_clr_err()
194 mb(); in polaris_machine_check()
195 mb(); in polaris_machine_check()
[all …]
H A Dsys_alcor.c42 mb(); in alcor_update_irq_hw()
63 *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb(); in alcor_mask_and_ack_irq()
64 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_mask_and_ack_irq()
73 *(vuip)GRU_INT_CLEAR = 0x80000000; mb(); in alcor_isa_mask_and_ack_irq()
74 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_isa_mask_and_ack_irq()
116 *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ in alcor_init_irq()
117 *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ in alcor_init_irq()
118 *(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */ in alcor_init_irq()
119 *(vuip)GRU_INT_CLEAR = 0; mb(); /* all clear */ in alcor_init_irq()
153 * 8 Interrupt Line A from slot 0
[all …]
/linux/Documentation/arch/x86/x86_64/
H A Dmm.rst20 from TB to GB and then MB/KB.
36 …0000800000000000 | +128 TB | 7fffffffffffffff | ~8 EB | ... huge, almost 63 bits wide hole of…
37 … | | | | virtual memory addresses up to the -8 EB
47 …8000000000000000 | -8 EB | ffff7fffffffffff | ~8 EB | ... huge, almost 63 bits wide hole of…
55 …ffff800000000000 | -128 TB | ffff87ffffffffff | 8 TB | ... guard hole, also reserved for hyp…
77 …ffffffff80000000 | -2 GB | ffffffff9fffffff | 512 MB | kernel text mapping, mapped to physic…
78 ffffffff80000000 |-2048 MB | | |
79 ffffffffa0000000 |-1536 MB | fffffffffeffffff | 1520 MB | module mapping space
80 ffffffffff000000 | -16 MB | | |
81 …FIXADDR_START | ~-11 MB | ffffffffff5fffff | ~0.5 MB | kernel-internal fixmap range, variable s…
[all …]
/linux/drivers/net/ethernet/apple/
H A Dmace.c31 #define N_RX_RING 8
35 #define RX_BUFLEN (ETH_FRAME_LEN + 8)
173 mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) | in mace_probe()
251 mp->chipid >> 8, mp->chipid & 0xff); in mace_probe()
319 volatile struct mace __iomem *mb = mp->mace; in mace_reset() local
325 out_8(&mb->biucc, SWRST); in mace_reset()
326 if (in_8(&mb->biucc) & SWRST) { in mace_reset()
337 out_8(&mb->imr, 0xff); /* disable all intrs for now */ in mace_reset()
338 i = in_8(&mb->ir); in mace_reset()
339 out_8(&mb->maccc, 0); /* turn off tx, rx */ in mace_reset()
[all …]
/linux/Documentation/fb/
H A Dmatroxfb.rst46 8 0x100 0x101 0x180 0x103 0x188
61 8 0x105 0x190 0x107 0x198 0x11C
75 8x8 0x1C0 0x108 0x10A 0x10B 0x10C
76 8x16 2, 3, 7 0x109
91 architectures there are some glitches for 24bpp videomodes. 8, 16 and 32bpp
125 memory usable for on-screen display (i.e. max. 8 MB).
162 - 0 -> 2x128Kx32 chips, 2MB onboard, probably sgram
163 - 1 -> 2x128Kx32 chips, 4MB onboard, probably sgram
164 - 2 -> 2x256Kx32 chips, 4MB onboard, probably sgram
165 - 3 -> 2x256Kx32 chips, 8MB onboard, probably sgram
[all …]
H A Dintel810.rst37 - Supports color depths of 8, 16, 24 and 32 bits per pixel
41 - Full and optimized hardware acceleration at 8, 16 and 24 bpp
88 select amount of system RAM in MB to allocate for the video memory
90 Recommendation: 1 - 4 MB.
96 Recommendation: 8
97 (default = 8)
123 select at what offset in MB of the logical memory to allocate the
126 offset (16 MB for a 64 MB aperture, 8 MB for a 32 MB aperture) will
127 avoid XFree86's usage and allows up to 7 MB/15 MB of framebuffer
129 (0 for maximum usage, 31/63 MB for the least amount). Note, an
[all …]
/linux/arch/mips/include/asm/sgi/
H A Dgio.h20 * There is 10MB of GIO address space for GIO64 slot devices
23 * 0 GFX 0x1f000000 - 0x1f3fffff 4MB
24 * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB
25 * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB
29 * - MISC 0x1fb00000 - 0x1fbfffff 1MB
32 * - RESERVED 0x18000000 - 0x1effffff 112MB
37 * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
38 * than 128 are 8 bits long, with the most significant 24 bits read from
43 * bit 7 0=GIO Product ID is 8 bits wide
45 * bits 8:15 manufacturer version for the product.
[all …]
/linux/arch/arc/plat-axs10x/
H A Daxs10x.c44 * | snps,dw-apb-intc (MB)| in axs10x_enable_gpio_intc_wire()
55 * DT hardware topology - connect MB intc directly to cpu intc in axs10x_enable_gpio_intc_wire()
94 char mb[32]; in axs10x_early_init() local
104 scnprintf(mb, 32, "MainBoard v%d", mb_rev); in axs10x_early_init()
105 axs10x_print_board_ver(CREG_MB_VER, mb); in axs10x_early_init()
121 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
122 * of which maps to a corresponding 256MB aperture in Target slave memory map.
124 * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
127 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
131 * MB AXI Tunnel Master, which also has a mem map setup
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/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi.h15 #define SRAM_BAR_SIZE 0x4000000ull /* 64MB */
16 #define CFG_BAR_SIZE 0x8000000ull /* 128MB */
19 #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
22 #define SRAM_SIZE 0x1400000 /* 20MB */
49 #define TPC_NUMBER_OF_ENGINES 8
51 #define DMA_NUMBER_OF_CHANNELS 8
57 #define NUMBER_OF_IF 8
/linux/net/can/
H A Dgw.c178 for (i = 0; i < CANFD_MAX_DLEN; i += 8) in mod_and_fddata()
186 for (i = 0; i < CANFD_MAX_DLEN; i += 8) in mod_or_fddata()
194 for (i = 0; i < CANFD_MAX_DLEN; i += 8) in mod_xor_fddata()
225 /* plain data length 0 .. 8 - that was easy */ in mod_store_ccdlc()
298 * relative to received dlc -1 .. -8 : in cgw_chk_csum_parms()
299 * e.g. for received dlc = 8 in cgw_chk_csum_parms()
302 * -8 => index = 0 (data[0]) in cgw_chk_csum_parms()
396 (cf->can_id >> 8 & 0xFF)]; in cgw_csum_crc8_rel()
423 (cf->can_id >> 8 & 0xFF)]; in cgw_csum_crc8_pos()
450 (cf->can_id >> 8 & 0xFF)]; in cgw_csum_crc8_neg()
[all …]
/linux/drivers/net/fddi/skfp/
H A Dsmt.c26 #define m_fc(mb) ((mb)->sm_data[0]) argument
72 static void smt_add_frame_len(SMbuf *mb, int len);
271 if (time - smc->sm.smt_last_lem >= TICKS_PER_SECOND*8) { in smt_event()
273 * Use 8 sec. for the time intervall, it simplifies the in smt_event()
352 /* If ratio is more than 5 in 8 seconds in smt_event()
460 void smt_received_pack(struct s_smc *smc, SMbuf *mb, int fs) in smt_received_pack() argument
468 switch (m_fc(mb)) { in smt_received_pack()
475 smt_free_mbuf(smc,mb) ; in smt_received_pack()
480 sm = smtod(mb,struct smt_header *) ; in smt_received_pack()
486 smt_free_mbuf(smc,mb) ; in smt_received_pack()
[all …]
/linux/drivers/eisa/
H A Deisa.ids246 CPQ5251 "Compaq 5/133 System Processor Board-2MB"
247 CPQ5253 "Compaq 5/166 System Processor Board-2MB"
248 CPQ5255 "Compaq 5/133 System Processor Board-1MB"
249 CPQ525D "Compaq 5/100 System Processor Board-1MB"
281 CPQ9018 "Compaq 486/33 Processor Board (8 MB)"
284 CPQ9036 "Compaq 486SX/25 Processor Board (8 MB)"
285 CPQ9037 "Compaq 486SX/16 Processor Board (8 MB)"
286 CPQ9038 "Compaq 486SX/33 Processor Board (8 MB)"
287 CPQ903C "Compaq 486SX/33 Processor Board (4 MB)"
296 CPQ9251 "Compaq 5/133 System Processor Board-2MB"
[all …]
/linux/tools/testing/selftests/mm/
H A Dcharge_reserved_hugetlb.sh92 mb=$(($kb / 1024))
93 echo $mb
96 MB=$(get_machine_hugepage_size)
97 if (( MB >= 1024 )); then
100 MB_DISPLAY=$((MB / 1024))
102 # For 2MB hugepages
103 UNIT="MB"
104 MB_DISPLAY=$MB
184 local expect_failure="$8"
294 local size=$(($1 * ${MB} * 102
[all...]
/linux/drivers/accel/habanalabs/include/goya/
H A Dgoya.h15 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
19 #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
22 #define SRAM_SIZE 0x32A0000 /* 50.625MB */
29 #define GOYA_MSIX_ENTRIES 8
39 #define TPC_MAX_NUM 8
/linux/tools/testing/selftests/cgroup/
H A Dtest_hugetlb_memcg.c15 /* mapping 8 MBs == 4 hugepages */
16 #define LENGTH (8UL*1024*1024)
105 if (current - old_current >= MB(2)) { in hugetlb_test_program()
118 if (current - old_current >= MB(2)) { in hugetlb_test_program()
127 expected_current = old_current + MB(2); in hugetlb_test_program()
130 ksft_print_msg("memory usage should increase by around 2MB.\n"); in hugetlb_test_program()
140 expected_current = old_current + MB(8); in hugetlb_test_program()
142 ksft_print_msg("memory usage should increase by around 8MB.\n"); in hugetlb_test_program()
215 ksft_print_msg("test_hugetlb_memcg requires 2MB hugepages\n"); in main()
/linux/Documentation/devicetree/bindings/pci/
H A Dfaraday,ftpci100.yaml84 be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB,
85 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
170 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2.h16 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
21 #define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/
22 #define CFG_REGION_SIZE 0xC000000ull /* 192MB */
24 #define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */
25 #define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */
26 #define STM_FLASH_SIZE 0x2000000ull /* 32MB */
29 #define SPI_FLASH_SIZE 0x1000000ull /* 16MB */
38 #define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */
41 #define SRAM_SIZE 0x3000000ull /* 48MB */
103 #define NUM_OF_RTR_PER_DCORE 8

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