Lines Matching +full:8 +full:mb
14 Rev 3.27.1, February 8, 2010, Michael Reed
77 Rev 3.23.31 June 8, 2003, Jes Sorensen
162 Rev 3.23.8 Beta September 29, 2001, Jes Sorensen
192 Rev 3.23.4 Beta August 8, 2001, Jes Sorensen
319 Rev. 1.20 June 8, 1999 DG, Qlogic
590 chksum += (*wptr >> 8) & 0xff; in qla1280_read_nvram()
602 chksum += (*wptr >> 8) & 0xff; in qla1280_read_nvram()
1110 uint16_t mb[MAILBOX_REGISTER_COUNT]; in qla1280_set_target_parameters() local
1119 mb[0] = MBC_SET_TARGET_PARAMETERS; in qla1280_set_target_parameters()
1120 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8); in qla1280_set_target_parameters()
1121 mb[2] = nv->bus[bus].target[target].parameter.renegotiate_on_error << 8; in qla1280_set_target_parameters()
1122 mb[2] |= nv->bus[bus].target[target].parameter.stop_queue_on_check << 9; in qla1280_set_target_parameters()
1123 mb[2] |= nv->bus[bus].target[target].parameter.auto_request_sense << 10; in qla1280_set_target_parameters()
1124 mb[2] |= nv->bus[bus].target[target].parameter.tag_queuing << 11; in qla1280_set_target_parameters()
1125 mb[2] |= nv->bus[bus].target[target].parameter.enable_sync << 12; in qla1280_set_target_parameters()
1126 mb[2] |= nv->bus[bus].target[target].parameter.enable_wide << 13; in qla1280_set_target_parameters()
1127 mb[2] |= nv->bus[bus].target[target].parameter.parity_checking << 14; in qla1280_set_target_parameters()
1128 mb[2] |= nv->bus[bus].target[target].parameter.disconnect_allowed << 15; in qla1280_set_target_parameters()
1131 mb[2] |= nv->bus[bus].target[target].ppr_1x160.flags.enable_ppr << 5; in qla1280_set_target_parameters()
1132 mb[3] = (nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8); in qla1280_set_target_parameters()
1133 mb[6] = (nv->bus[bus].target[target].ppr_1x160.flags.ppr_options << 8) | in qla1280_set_target_parameters()
1137 mb[3] = (nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8); in qla1280_set_target_parameters()
1139 mb[3] |= nv->bus[bus].target[target].sync_period; in qla1280_set_target_parameters()
1141 status = qla1280_mailbox_command(ha, mr, mb); in qla1280_set_target_parameters()
1145 mb[0] = MBC_SET_DEVICE_QUEUE; in qla1280_set_target_parameters()
1146 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8); in qla1280_set_target_parameters()
1147 mb[1] |= lun; in qla1280_set_target_parameters()
1148 mb[2] = nv->bus[bus].max_queue_depth; in qla1280_set_target_parameters()
1149 mb[3] = nv->bus[bus].target[target].execution_throttle; in qla1280_set_target_parameters()
1150 status |= qla1280_mailbox_command(ha, 0x0f, mb); in qla1280_set_target_parameters()
1169 * as the default queue depth. Otherwise, we use either 4 or 8 as the
1547 uint16_t mb[MAILBOX_REGISTER_COUNT]; in qla1280_chip_diag() local
1627 mb[0] = MBC_MAILBOX_REGISTER_TEST; in qla1280_chip_diag()
1628 mb[1] = 0xAAAA; in qla1280_chip_diag()
1629 mb[2] = 0x5555; in qla1280_chip_diag()
1630 mb[3] = 0xAA55; in qla1280_chip_diag()
1631 mb[4] = 0x55AA; in qla1280_chip_diag()
1632 mb[5] = 0xA5A5; in qla1280_chip_diag()
1633 mb[6] = 0x5A5A; in qla1280_chip_diag()
1634 mb[7] = 0x2525; in qla1280_chip_diag()
1636 status = qla1280_mailbox_command(ha, 0xff, mb); in qla1280_chip_diag()
1640 if (mb[1] != 0xAAAA || mb[2] != 0x5555 || mb[3] != 0xAA55 || in qla1280_chip_diag()
1641 mb[4] != 0x55AA || mb[5] != 0xA5A5 || mb[6] != 0x5A5A || in qla1280_chip_diag()
1642 mb[7] != 0x2525) { in qla1280_chip_diag()
1662 uint16_t mb[MAILBOX_REGISTER_COUNT], i; in qla1280_load_firmware_pio() local
1678 mb[0] = MBC_WRITE_RAM_WORD; in qla1280_load_firmware_pio()
1679 mb[1] = risc_address + i; in qla1280_load_firmware_pio()
1680 mb[2] = __le16_to_cpu(fw_data[i]); in qla1280_load_firmware_pio()
1682 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1711 uint16_t mb[MAILBOX_REGISTER_COUNT], cnt; in qla1280_load_firmware_dma() local
1752 mb[0] = LOAD_CMD; in qla1280_load_firmware_dma()
1753 mb[1] = risc_address; in qla1280_load_firmware_dma()
1754 mb[4] = cnt; in qla1280_load_firmware_dma()
1755 mb[3] = ha->request_dma & 0xffff; in qla1280_load_firmware_dma()
1756 mb[2] = (ha->request_dma >> 16) & 0xffff; in qla1280_load_firmware_dma()
1757 mb[7] = upper_32_bits(ha->request_dma) & 0xffff; in qla1280_load_firmware_dma()
1758 mb[6] = upper_32_bits(ha->request_dma) >> 16; in qla1280_load_firmware_dma()
1760 __func__, mb[0], in qla1280_load_firmware_dma()
1762 mb[6], mb[7], mb[2], mb[3]); in qla1280_load_firmware_dma()
1763 err = qla1280_mailbox_command(ha, CMD_ARGS, mb); in qla1280_load_firmware_dma()
1771 mb[0] = DUMP_CMD; in qla1280_load_firmware_dma()
1772 mb[1] = risc_address; in qla1280_load_firmware_dma()
1773 mb[4] = cnt; in qla1280_load_firmware_dma()
1774 mb[3] = p_tbuf & 0xffff; in qla1280_load_firmware_dma()
1775 mb[2] = (p_tbuf >> 16) & 0xffff; in qla1280_load_firmware_dma()
1776 mb[7] = upper_32_bits(p_tbuf) & 0xffff; in qla1280_load_firmware_dma()
1777 mb[6] = upper_32_bits(p_tbuf) >> 16; in qla1280_load_firmware_dma()
1779 err = qla1280_mailbox_command(ha, CMD_ARGS, mb); in qla1280_load_firmware_dma()
1814 uint16_t mb[MAILBOX_REGISTER_COUNT]; in qla1280_start_firmware() local
1821 mb[0] = MBC_VERIFY_CHECKSUM; in qla1280_start_firmware()
1822 /* mb[1] = ql12_risc_code_addr01; */ in qla1280_start_firmware()
1823 mb[1] = ha->fwstart; in qla1280_start_firmware()
1824 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_start_firmware()
1832 mb[0] = MBC_EXECUTE_FIRMWARE; in qla1280_start_firmware()
1833 mb[1] = ha->fwstart; in qla1280_start_firmware()
1834 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_start_firmware()
1879 uint16_t mb[MAILBOX_REGISTER_COUNT]; in qla1280_init_rings() local
1892 /* mb[0] = MBC_INIT_REQUEST_QUEUE; */ in qla1280_init_rings()
1893 mb[0] = MBC_INIT_REQUEST_QUEUE_A64; in qla1280_init_rings()
1894 mb[1] = REQUEST_ENTRY_CNT; in qla1280_init_rings()
1895 mb[3] = ha->request_dma & 0xffff; in qla1280_init_rings()
1896 mb[2] = (ha->request_dma >> 16) & 0xffff; in qla1280_init_rings()
1897 mb[4] = 0; in qla1280_init_rings()
1898 mb[7] = upper_32_bits(ha->request_dma) & 0xffff; in qla1280_init_rings()
1899 mb[6] = upper_32_bits(ha->request_dma) >> 16; in qla1280_init_rings()
1902 &mb[0]))) { in qla1280_init_rings()
1906 /* mb[0] = MBC_INIT_RESPONSE_QUEUE; */ in qla1280_init_rings()
1907 mb[0] = MBC_INIT_RESPONSE_QUEUE_A64; in qla1280_init_rings()
1908 mb[1] = RESPONSE_ENTRY_CNT; in qla1280_init_rings()
1909 mb[3] = ha->response_dma & 0xffff; in qla1280_init_rings()
1910 mb[2] = (ha->response_dma >> 16) & 0xffff; in qla1280_init_rings()
1911 mb[5] = 0; in qla1280_init_rings()
1912 mb[7] = upper_32_bits(ha->response_dma) & 0xffff; in qla1280_init_rings()
1913 mb[6] = upper_32_bits(ha->response_dma) >> 16; in qla1280_init_rings()
1916 &mb[0]); in qla1280_init_rings()
2053 nv->bus[bus].config_2.async_data_setup_time = 8; in qla1280_set_defaults()
2065 uint16_t mb[MAILBOX_REGISTER_COUNT]; in qla1280_config_target() local
2070 mb[0] = MBC_SET_TARGET_PARAMETERS; in qla1280_config_target()
2071 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8); in qla1280_config_target()
2078 mb[2] = (TP_RENEGOTIATE | TP_AUTO_REQUEST_SENSE | TP_TAGGED_QUEUE in qla1280_config_target()
2082 mb[3] = nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8; in qla1280_config_target()
2084 mb[3] = nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8; in qla1280_config_target()
2085 mb[3] |= nv->bus[bus].target[target].sync_period; in qla1280_config_target()
2086 status = qla1280_mailbox_command(ha, 0x0f, mb); in qla1280_config_target()
2108 mb[0] = MBC_SET_DEVICE_QUEUE; in qla1280_config_target()
2109 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8); in qla1280_config_target()
2110 mb[1] |= lun; in qla1280_config_target()
2111 mb[2] = nv->bus[bus].max_queue_depth; in qla1280_config_target()
2112 mb[3] = nv->bus[bus].target[target].execution_throttle; in qla1280_config_target()
2113 status |= qla1280_mailbox_command(ha, 0x0f, mb); in qla1280_config_target()
2123 uint16_t mb[MAILBOX_REGISTER_COUNT]; in qla1280_config_bus() local
2132 mb[0] = MBC_SET_INITIATOR_ID; in qla1280_config_bus()
2133 mb[1] = bus ? ha->bus_settings[bus].id | BIT_7 : in qla1280_config_bus()
2135 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_config_bus()
2157 uint16_t mb[MAILBOX_REGISTER_COUNT]; in qla1280_nvram_config() local
2218 mb[0] = MBC_SET_SYSTEM_PARAMETER; in qla1280_nvram_config()
2219 mb[1] = nv->isp_parameter; in qla1280_nvram_config()
2220 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_nvram_config()
2224 mb[0] = MBC_SET_CLOCK_RATE; in qla1280_nvram_config()
2225 mb[1] = 40; in qla1280_nvram_config()
2226 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_nvram_config()
2230 mb[0] = MBC_SET_FIRMWARE_FEATURES; in qla1280_nvram_config()
2231 mb[1] = nv->firmware_feature.f.enable_fast_posting; in qla1280_nvram_config()
2232 mb[1] |= nv->firmware_feature.f.report_lvd_bus_transition << 1; in qla1280_nvram_config()
2233 mb[1] |= nv->firmware_feature.f.disable_synchronous_backoff << 5; in qla1280_nvram_config()
2234 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_nvram_config()
2237 mb[0] = MBC_SET_RETRY_COUNT; in qla1280_nvram_config()
2238 mb[1] = nv->bus[0].retry_count; in qla1280_nvram_config()
2239 mb[2] = nv->bus[0].retry_delay; in qla1280_nvram_config()
2240 mb[6] = nv->bus[1].retry_count; in qla1280_nvram_config()
2241 mb[7] = nv->bus[1].retry_delay; in qla1280_nvram_config()
2243 BIT_1 | BIT_0, &mb[0]); in qla1280_nvram_config()
2246 mb[0] = MBC_SET_ASYNC_DATA_SETUP; in qla1280_nvram_config()
2247 mb[1] = nv->bus[0].config_2.async_data_setup_time; in qla1280_nvram_config()
2248 mb[2] = nv->bus[1].config_2.async_data_setup_time; in qla1280_nvram_config()
2249 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]); in qla1280_nvram_config()
2252 mb[0] = MBC_SET_ACTIVE_NEGATION; in qla1280_nvram_config()
2253 mb[1] = 0; in qla1280_nvram_config()
2255 mb[1] |= BIT_5; in qla1280_nvram_config()
2257 mb[1] |= BIT_4; in qla1280_nvram_config()
2258 mb[2] = 0; in qla1280_nvram_config()
2260 mb[2] |= BIT_5; in qla1280_nvram_config()
2262 mb[2] |= BIT_4; in qla1280_nvram_config()
2263 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb); in qla1280_nvram_config()
2265 mb[0] = MBC_SET_DATA_OVERRUN_RECOVERY; in qla1280_nvram_config()
2266 mb[1] = 2; /* Reset SCSI bus and return all outstanding IO */ in qla1280_nvram_config()
2267 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_nvram_config()
2270 mb[0] = MBC_SET_PCI_CONTROL; in qla1280_nvram_config()
2271 mb[1] = BIT_1; /* Data DMA Channel Burst Enable */ in qla1280_nvram_config()
2272 mb[2] = BIT_1; /* Command DMA Channel Burst Enable */ in qla1280_nvram_config()
2273 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb); in qla1280_nvram_config()
2275 mb[0] = MBC_SET_TAG_AGE_LIMIT; in qla1280_nvram_config()
2276 mb[1] = 8; in qla1280_nvram_config()
2277 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_nvram_config()
2280 mb[0] = MBC_SET_SELECTION_TIMEOUT; in qla1280_nvram_config()
2281 mb[1] = nv->bus[0].selection_timeout; in qla1280_nvram_config()
2282 mb[2] = nv->bus[1].selection_timeout; in qla1280_nvram_config()
2283 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb); in qla1280_nvram_config()
2318 dprintk(8, "qla1280_get_nvram_word: exiting normally NVRAM data = " in qla1280_get_nvram_word()
2404 * mb = data pointer for mailbox registers.
2407 * mb[MAILBOX_REGISTER_COUNT] = returned mailbox data.
2413 qla1280_mailbox_command(struct scsi_qla_host *ha, uint8_t mr, uint16_t *mb) in qla1280_mailbox_command() argument
2435 iptr = mb; in qla1280_mailbox_command()
2468 mb[0], ha->mailbox_out[0], RD_REG_WORD(®->istatus)); in qla1280_mailbox_command()
2479 optr = mb; in qla1280_mailbox_command()
2488 "0x%x ****\n", mb[0]); in qla1280_mailbox_command()
2540 uint16_t mb[MAILBOX_REGISTER_COUNT]; in qla1280_bus_reset() local
2551 mb[0] = MBC_BUS_RESET; in qla1280_bus_reset()
2552 mb[1] = reset_delay; in qla1280_bus_reset()
2553 mb[2] = (uint16_t) bus; in qla1280_bus_reset()
2554 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]); in qla1280_bus_reset()
2600 uint16_t mb[MAILBOX_REGISTER_COUNT]; in qla1280_device_reset() local
2605 mb[0] = MBC_ABORT_TARGET; in qla1280_device_reset()
2606 mb[1] = (bus ? (target | BIT_7) : target) << 8; in qla1280_device_reset()
2607 mb[2] = 1; in qla1280_device_reset()
2608 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]); in qla1280_device_reset()
2634 uint16_t mb[MAILBOX_REGISTER_COUNT]; in qla1280_abort_command() local
2646 mb[0] = MBC_ABORT_COMMAND; in qla1280_abort_command()
2647 mb[1] = (bus ? target | BIT_7 : target) << 8 | lun; in qla1280_abort_command()
2648 mb[2] = handle >> 16; in qla1280_abort_command()
2649 mb[3] = handle & 0xffff; in qla1280_abort_command()
2650 status = qla1280_mailbox_command(ha, 0x0f, &mb[0]); in qla1280_abort_command()
2818 memset(((char *)pkt + 8), 0, (REQUEST_ENTRY_SIZE - 8)); in qla1280_64bit_start_scsi()
3073 memset(((char *)pkt + 8), 0, (REQUEST_ENTRY_SIZE - 8)); in qla1280_32bit_start_scsi()
3469 /* dprintk(1, "qla1280_isr: default case of switch MB \n"); */ in qla1280_isr()
3883 uint16_t mb[MAILBOX_REGISTER_COUNT]; in qla1280_get_target_parameters() local
3891 mb[0] = MBC_GET_TARGET_PARAMETERS; in qla1280_get_target_parameters()
3892 mb[1] = (uint16_t) (bus ? target | BIT_7 : target); in qla1280_get_target_parameters()
3893 mb[1] <<= 8; in qla1280_get_target_parameters()
3895 &mb[0]); in qla1280_get_target_parameters()
3899 if (mb[3] != 0) { in qla1280_get_target_parameters()
3901 (mb[3] & 0xff), (mb[3] >> 8)); in qla1280_get_target_parameters()
3902 if (mb[2] & BIT_13) in qla1280_get_target_parameters()
3904 if ((mb[2] & BIT_5) && ((mb[6] >> 8) & 0xff) >= 2) in qla1280_get_target_parameters()
3922 printk(KERN_DEBUG " 0 1 2 3 4 5 6 7 8 9 Ah " in __qla1280_dump_buffer()